Signal Integrity for High-Speed Digital

01 — The Problem

Why Signal Integrity Matters

At low data rates (<100 Mbps), a PCB trace is just a wire — resistance matters, nothing else. At 1 Gbps, the trace is a transmission line and reflections from impedance discontinuities corrupt the signal. At 10 Gbps, the PCB trace itself acts as a lowpass filter — attenuating the high-frequency content of the signal and causing inter-symbol interference (ISI). At 56 Gbps (PCIe Gen 5, USB4), the trace loss is so severe that active equalization in both the transmitter and receiver is mandatory.

The Fundamental SI Equation

f_knee = 0.35/t_r (bandwidth of digital signal, t_r = 10–90% rise time)
t_r ≈ 0.35/BW (rise time from bandwidth limit)
At 10 Gbps NRZ: bit period T=100 ps, t_r ≈ 0.35×T = 35 ps, f_knee = 0.35/35ps = 10 GHz
Rule of thumb: transmission line effects become critical when trace length > λ/10 at f_knee
λ at 10 GHz on FR4 (εr=4.2): λ = c/(f√εr) = 14.6 mm → critical length = 1.46 mm
Any trace >1.46 mm at 10 Gbps needs controlled impedance and termination!

SI is RF engineering in disguise: A 10 Gbps serial link has significant signal content up to 10 GHz — firmly in the microwave regime. Microstrip impedance, skin effect loss, dielectric loss tan δ, reflections from discontinuities, via stubs, connector SMA launches — all the RF phenomena you've studied apply directly to high-speed digital design.

02 — Eye Diagrams

Eye Diagrams

An eye diagram is created by superimposing thousands of bit transitions, aligned to the bit clock, on top of each other. The resulting pattern looks like an open eye when the channel is clean — and progressively closes as jitter, noise, ISI and crosstalk degrade the signal. The eye diagram is the primary SI characterisation tool.

Eye Diagram Parameters

Parameter	Definition	Units	Typical Mask Limit
Eye Height	Vertical opening at sampling instant — signal margin vs noise	mV or % UI	>100–200 mV for most standards
Eye Width	Horizontal opening — timing margin vs jitter	ps or % UI	>0.5–0.7 UI (UI = 1 bit period)
Eye Mask	Forbidden zone in centre of eye — standard defines polygon shape	UI × % swing	No waveform points may enter mask
Rise/Fall Time	10–90% transition time of eye edges	ps	Typically 0.2–0.4 UI
Crossing Level	Voltage at bit transitions — ideally 50% of swing	%	40–60% (asymmetry indicates ISI)
Waveform Jitter	Variation in crossing time vs ideal clock	ps RMS or pp	Standard-dependent (see jitter section)
Extinction Ratio	Ratio of high level to low level optical power — optical links only	dB	>6 dB (10 GbE), >8.2 dB (100 GbE)

Eye mask is the pass/fail criterion: Every standard (PCIe, USB, HDMI, Ethernet) defines an eye mask polygon. No waveform sample may fall inside the mask. Mask violations cause BER degradation — each mask hit roughly corresponds to 1 bit error per million transitions. A BERT (bit error rate tester) confirms the actual BER at the target point on the eye mask.

03 — Jitter Analysis

Jitter Decomposition

Jitter is the deviation of a signal edge from its ideal position in time. It degrades eye width and ultimately increases bit error rate (BER). Understanding jitter composition is essential for separating curable (deterministic) from incurable (random) jitter components.

Jitter Components

Jitter Decomposition

TJ = RJ ⊗ DJ (total jitter = convolution of random and deterministic)
TJ@BER = DJ_pp + 2·n·σ_RJ (n = Q-factor from BER target)
n at BER=10⁻¹²: n=7.0 · n at BER=10⁻¹⁵: n=7.9 · n at BER=10⁻³: n=3.1
Example: RJ=1 ps RMS, DJ=10 ps pp, BER target=10⁻¹²:
TJ = 10 + 2×7.0×1 = 10+14 = 24 ps pp at BER=10⁻¹²

DJ = ISI_jitter + PJ (periodic) + DDJ (data dependent) + DCD (duty cycle distortion)
RJ = Gaussian noise sources: thermal, shot, power supply noise on clock path

Jitter Type	Symbol	Source	Cure
Total Jitter	TJ	All sources combined	TJ budget across full channel
Random Jitter	RJ	Thermal noise, shot noise — Gaussian, unbounded	Lower noise PLL, better power supply
Deterministic Jitter	DJ	Bounded, pattern-dependent or periodic	Equalization, better channel design
Data Dependent Jitter	DDJ	ISI — previous bit patterns affect current edge	Equalization (CTLE, DFE)
Periodic Jitter	PJ	Switching regulators, PLLs — sinusoidal jitter	Better power supply decoupling, spread-spectrum clocking
Duty Cycle Distortion	DCD	DC offset → different rise/fall zero-crossing times	AC coupling + well-matched differential pair

Jitter Budget — PCIe Gen 4 Example

Example 1 — PCIe Gen 4 (16 GT/s) jitter budget at BER=10⁻¹²

UI (unit interval) = 1/16G = 62.5 ps

TX RJ budget: 0.6 ps RMS · TX DJ budget: 6 ps pp · TX TJ = 6+2×7×0.6 = 14.4 ps = 0.23 UI

Channel ISI/crosstalk contribution: 8 ps pp deterministic

RX RJ budget: 0.3 ps RMS · RX DJ: 4 ps pp

Total TJ = 14.4+8+(4+2×7×0.3) = 14.4+8+8.2 = 30.6 ps pp = 0.49 UI

Eye width at BER=10⁻¹²: 62.5−30.6 = 31.9 ps = 0.51 UI

PCIe Gen 4 spec requires eye width > 0.27 UI → margin = 0.24 UI = 15 ps ✓

✓ Eye width = 0.51 UI at BER=10⁻¹² — 0.24 UI margin above PCIe Gen 4 minimum. The ISI from the channel is the largest single contributor — target for equalization.

04 — Loss & ISI

ISI & Channel Loss

Inter-Symbol Interference (ISI) occurs when a signal transition spreads in time due to channel filtering, causing energy from one bit to contaminate neighbouring bits. ISI closes the eye vertically and horizontally. The two dominant loss mechanisms in PCB traces are skin effect loss and dielectric loss.

Skin Effect Loss

α_c = R_s/(2·Z_0·W) dB/m (conductor loss, R_s = surface resistance)
R_s = √(πf·μ₀/σ) = 1/σδ (Ω/□, increases as √f)
Skin depth δ = 66.5/√f[Hz] μm (copper) · R_s(copper at 10 GHz) = 0.026 Ω/□
Example: 100 μm wide, 35 μm thick copper trace at 10 GHz:
R_s=0.026 Ω/□, α_c = 0.026/(2×50×100μ) ≈ 2.6 dB/m

Dielectric Loss

α_d = π·f·√εr·tan(δ)/c Np/m → ×8.686 for dB/m
Increases linearly with frequency (unlike conductor loss which goes as √f)
FR4: tan δ = 0.02 · Rogers RO4350B: tan δ = 0.0037 · Megtron-7: tan δ = 0.002
Example: 50 Ω microstrip on FR4 (εr=4.2, tan δ=0.02) at 10 GHz:
α_d = π×10⁹×√4.2×0.02/(3×10⁸) × 8.686 = 9.7 dB/m
On RO4350B (tan δ=0.0037): α_d = 1.8 dB/m — 5.4× better!

Example 2 — Total channel loss at 10 GHz for 20 cm FR4 trace

α_c(10 GHz) ≈ 2.6 dB/m · α_d(10 GHz) ≈ 9.7 dB/m → total = 12.3 dB/m

20 cm trace: loss = 12.3×0.20 = 2.46 dB at 10 GHz (Nyquist for 20 Gbps NRZ)

At 1 GHz: α_c ≈ 0.82 dB/m, α_d ≈ 0.97 dB/m → total = 1.79 dB/m × 0.20 = 0.36 dB

Channel is a lowpass filter: passes low frequencies, attenuates high → ISI closes eye

Same trace on Rogers (tan δ=0.0037): total = (2.6+1.8)×0.20 = 0.88 dB — 1.58 dB better

✓ FR4 trace losses at 10 GHz are severe — 2.46 dB for just 20 cm. This is why PCIe Gen 4/5 requires pre-emphasis at the transmitter and equalization at the receiver. Upgrading to low-loss laminates (Megtron-6/7, RO4350B) recovers 1–2 dB loss per unit length.

Laminate	Dk (εr)	Df (tan δ)	Loss @10 GHz	Cost	Common Use
Standard FR4	4.2–4.5	0.018–0.025	9–12 dB/m	$1×	<2 Gbps, cost-sensitive
Isola I-Tera MT40	3.45	0.004	3.2 dB/m	$3×	PCIe Gen 3/4, 10G Ethernet
Panasonic Megtron-6	3.7	0.0025	2.8 dB/m	$4×	PCIe Gen 4/5, 25G/100G
Panasonic Megtron-7	3.3	0.002	2.2 dB/m	$5×	PCIe Gen 6, 400G Ethernet
Rogers RO4350B	3.66	0.0037	2.5 dB/m	$6×	RF PCB, microwave passives
Rogers RT/Duroid 5880	2.2	0.0009	1.2 dB/m	$15×	mm-Wave, Ka-band, lab

05 — Equalization

Pre-emphasis & Equalization

Equalization is the process of compensating for channel frequency response — boosting attenuated high frequencies to flatten the overall transfer function. Modern SerDes devices implement equalization both at the transmitter (TX pre-emphasis) and receiver (RX equalization) with several different filter topologies.

TX Pre-emphasis / De-emphasis (FFE)

Feed-Forward Equalization (FFE) at the transmitter applies a FIR filter to the outgoing data stream — boosting high-frequency content (pre-emphasis) or de-emphasising the DC level (de-emphasis) relative to the transition edges. FFE compensates for the known frequency response of the channel before the signal enters the channel.

TX FFE (3-tap example)

y[n] = c₋₁·x[n+1] + c₀·x[n] + c₁·x[n−1] (pre-cursor, main, post-cursor)
Constraint: |c₋₁| + |c₀| + |c₁| = 1 (normalised to maintain output power)
Common setting for 10 cm FR4 trace at 10 Gbps:
c₋₁=0, c₀=0.7, c₁=−0.3 → de-emphasis = 20·log₁₀(0.4/0.7+0.3) = −6 dB
De-emphasis reduces main cursor (c₀) while boosting edge transitions relative to steady-state

De-emphasis vs pre-emphasis: De-emphasis reduces the steady-state signal level — the transmitter outputs a smaller voltage between transitions. This effectively boosts the edge transition relative to the steady state. The result is the same — high-frequency content is boosted relative to low-frequency — but de-emphasis is easier to implement and maintains the peak voltage at the transition edge.

RX Equalization — CTLE and DFE

Continuous Time Linear Equalizer (CTLE) is an analog high-pass filter in the receiver input stage that boosts high frequencies to compensate for channel loss. It is always active and adds to receiver noise at high frequencies. Decision Feedback Equalization (DFE) uses previously decided bits to subtract their ISI contribution from the current bit decision.

Equalizer	Type	Compensates	Limitation
TX FFE	Linear, FIR, transmitter	Pre- and post-cursor ISI	Reduces signal amplitude — noise margin cost
RX CTLE	Linear, analog HPF, receiver	Channel loss (frequency response)	Boosts high-frequency noise — SNR trade-off
RX DFE	Non-linear, decision feedback	Post-cursor ISI only	Error propagation if previous decision wrong
PAM4 DSP equalizer	Digital, adaptive FIR	ISI, crosstalk, reflections	High power consumption, latency

CTLE Transfer Function

H_CTLE(s) = A₀·(1 + s/ω_z) / (1 + s/ω_p) (single zero, single pole highpass peaking)
Peak gain at ω → ∞: A₀·(ω_p/ω_z) · DC gain: A₀
Peaking = 20·log₁₀(ω_p/ω_z) dB at Nyquist frequency
Typical CTLE peaking: 3–15 dB at 5–15 GHz depending on channel loss
PCIe Gen 4 CTLE: up to 15 dB peaking at 8 GHz (Nyquist for 16 GT/s)

06 — SerDes Architecture

SerDes Architecture

A SerDes (Serializer/Deserializer) converts a wide parallel data bus to a high-speed serial stream for transmission across a channel, then back to parallel at the receiver. Every high-speed interface (PCIe, USB 3, SATA, HDMI, 25G/100G Ethernet) is built on SerDes technology.

Block	TX Function	RX Function
PLL / Clock multiplier	Multiply reference clock to bit rate	CDR (clock and data recovery) — extract clock from data
Encoder	8b10b, 64b66b, 128b130b — DC balance, run length	Decoder — remove encoding overhead
Serializer / MUX	N:1 parallel-to-serial	1:N serial-to-parallel (deserializer)
FFE / Pre-emphasis	FIR filter on output data	CTLE + DFE at input
Driver	High-speed CML or LVDS output driver	Input termination (100 Ω diff)
Sampler / Slicer	—	Data and clock samplers at recovered clock edge

CDR is the most critical RX block: Clock and Data Recovery (CDR) extracts the transmitter clock from the received data stream — there is no clock transmitted separately in any modern serial interface. The CDR uses a Phase-Locked Loop (PLL) that locks to the zero-crossings in the data. CDR bandwidth determines jitter tracking vs jitter filtering: narrow bandwidth CDR filters most jitter but cannot track wander; wide bandwidth CDR tracks transmitter jitter but doesn't filter it.

Interface	Bit Rate	Encoding	Equalization	Channel Loss Budget
USB 3.2 Gen 2	10 Gbps	128b132b	TX FFE + RX CTLE	12 dB at 5 GHz
PCIe Gen 4	16 GT/s	128b130b	TX FFE (3-tap) + RX CTLE + DFE	28 dB at 8 GHz
PCIe Gen 5	32 GT/s	128b130b	TX FFE (5-tap) + RX CTLE + DFE	36 dB at 16 GHz
25G Ethernet	25.78 Gbps	64b66b	TX FFE + RX CTLE	20 dB at 12.89 GHz
100G Ethernet (4×25G)	4×25.78 Gbps	64b66b	TX FFE + RX CTLE	20 dB per lane
400G Ethernet (PAM4)	4×106 Gbps	PAM4 + RS-FEC	DSP FFE + CTLE + DFE	22 dB at 26.56 GHz

07 — Crosstalk

Crosstalk — NEXT & FEXT

Crosstalk is electromagnetic coupling between adjacent signal lines — a signal on one trace induces an unwanted voltage on a neighbouring trace. Two types: NEXT (Near-End CrossTalk) — noise coupled back to the transmitter end of the victim line, and FEXT (Far-End CrossTalk) — noise coupled to the receiver end. At multi-gigabit speeds, crosstalk is often the dominant SI impairment.

Crosstalk Coefficients

K_NEXT = (1/4)·(C_m/C₀ + L_m/L₀) (NEXT coupling coefficient)
K_FEXT = (T_d/2)·(C_m/C₀ − L_m/L₀) (FEXT coefficient, T_d=delay of coupled region)
C_m = mutual capacitance, L_m = mutual inductance, C₀/L₀ = self capacitance/inductance per unit length
V_NEXT = K_NEXT · ΔV/Δt · t_r · V_FEXT = K_FEXT · ΔV/t_r
NEXT (dB) = 20·log₁₀(V_NEXT/V_source)

Crosstalk Worked Example

Example 3 — FEXT between two 50 Ω microstrips, 100 μm spacing, 10 cm long, 5 Gbps

Coupling parameters for 100 μm spacing on 20 mil FR4: C_m/C₀ ≈ 0.08, L_m/L₀ ≈ 0.06

T_d = 10 cm × √εr_eff/c = 0.1 × √3.5/(3×10⁸) = 624 ps

K_FEXT = (T_d/2)×(C_m/C₀−L_m/L₀) = (312ps)×(0.08−0.06) = 312×0.02 = 6.24 ps

Rise time at 5 Gbps NRZ: t_r ≈ 0.35/5G×0.25 = 70 ps (0.35 UI)

V_FEXT/V = K_FEXT/t_r = 6.24ps/70ps = 8.9% of swing = −21 dB

Fix: increase spacing to 200 μm → C_m/C₀≈0.03, L_m/L₀≈0.025 → K_FEXT = 312×0.005 = 1.56 ps → V_FEXT=2.2% = −33 dB

✓ Doubling trace spacing reduces FEXT by 12 dB. The 3W rule (trace spacing ≥ 3× trace width centre-to-centre) ensures FEXT < −30 dB for most standard requirements. At 56 Gbps PAM4, tighter FEXT budgets require 4W–5W spacing or differential pairs with ground shielding between them.

Crosstalk Mitigation	NEXT Impact	FEXT Impact	Cost
Increase trace spacing (3W rule)	−12 dB per 2× spacing	−12 dB per 2× spacing	Board area
Ground guard traces	−20 dB additional	−15 dB additional	2× trace area
Buried stripline (vs microstrip)	−15 dB vs microstrip	−10 dB vs microstrip	Layer count
Shorten coupled length	Moderate reduction	Linear reduction with length	Route optimisation
Differential routing	Cancels common-mode NEXT	Cancels common-mode FEXT	Matched routing requirement
Orthogonal routing (layers)	Eliminates layer-to-layer	Eliminates layer-to-layer	More layers

08 — TDR

TDR Impedance Profiling

Time Domain Reflectometry (TDR) launches a fast step edge into a transmission line and measures the reflected waveform. Impedance discontinuities (vias, connectors, width changes) create partial reflections that appear at delays proportional to their distance from the TDR port. TDR is the primary tool for measuring controlled-impedance traces and diagnosing SI problems.

TDR Fundamentals

Γ(t) = V_reflected(t)/V_incident (reflection coefficient vs time)
Z(t) = Z_0·(1+Γ(t))/(1−Γ(t)) (impedance profile along line)
d = v_p·t/2 = c·t/(2√εr_eff) (distance from TDR port to discontinuity)
Spatial resolution: Δd = v_p·t_r/2 (two discontinuities within Δd are unresolved)
For 20 ps rise time TDR on FR4: Δd = (c/√3.5)×20ps/2 = 1.6 mm

TDR Signature	Reflection Shape	Cause
Inductive discontinuity	Positive spike then returns to baseline	Via stub, bond wire, connector pin
Capacitive discontinuity	Negative dip then returns to baseline	Via pad, SMD pad, ESD diode
High-Z section	Sustained positive step	Narrow trace, no ground plane
Low-Z section	Sustained negative step	Wide trace, ground pour, capacitive stub
Open circuit	Reflection = +1 (doubles incident)	Break in trace, missing solder joint
Short circuit	Reflection = −1 (cancels incident)	Solder bridge, trace short

Group Delay, TDR & SI Tool →

09 — Channel Link Budget

Channel Link Budget

A channel link budget allocates the available eye margin across all loss and impairment contributors. It is the SI equivalent of an RF link budget — if any contributor exceeds its allocation, the margin goes negative and the BER target is not met.

PCIe Gen 4 (16 GT/s) Channel Link Budget

Example 4 — PCIe Gen 4 channel link budget

Available budget: PCIe Gen 4 eye height must be >15 mV after equalization, signal swing = 800 mV pp diff

TX output amplitude: 800 mV pp diff

Connector insertion loss (×2 connectors): 3 dB total → −3 dB

PCB trace loss (20 cm Megtron-6 at 8 GHz): 0.56 dB/m × 0.20 m → −0.11 dB × 20 = wait ... trace loss at Nyquist 8 GHz: ≈28 dB/m total → 5.6 dB

Via stubs (×4 vias, each −0.5 dB): −2 dB

Crosstalk (FEXT, 3W spacing): −1.5 dB equivalent eye closure

TX FFE (3-tap pre-emphasis): +8 dB recovery

RX CTLE (12 dB peaking): +9 dB recovery

RX DFE (2 taps): +3 dB recovery

Net: 800 − losses + equalization = eye height > 15 mV ✓ (spec requires)

✓ PCIe Gen 4 requires 20+ dB of channel equalisation for a real backplane. Without FFE+CTLE+DFE, the channel would fail. This is why PCIe Gen 4/5 retimers (re-clocking chips) are used for backplane distances >40 cm.

10 — Standards Reference

High-Speed Interface Standards

Standard	Rate	Encoding	Eye Height	Eye Width	Channel Loss
USB 3.2 Gen 1	5 Gbps	8b10b	>100 mV	>0.5 UI	<12 dB @2.5 GHz
USB 3.2 Gen 2	10 Gbps	128b132b	>50 mV	>0.5 UI	<14 dB @5 GHz
PCIe Gen 3	8 GT/s	128b130b	>15 mV	>0.27 UI	<20 dB @4 GHz
PCIe Gen 4	16 GT/s	128b130b	>15 mV	>0.27 UI	<28 dB @8 GHz
PCIe Gen 5	32 GT/s	128b130b	>15 mV	>0.22 UI	<36 dB @16 GHz
HDMI 2.1	12 Gbps/lane	16b18b+FRL	>100 mV	>0.45 UI	<17 dB
SATA III	6 Gbps	8b10b	>200 mV	>0.4 UI	<8 dB @3 GHz
100G-SR4 (4×25G)	25.78 Gbps	64b66b	>100 mV	>0.3 UI	<20 dB

Signal Integrity Tool — TDR, Group Delay, Passivity → S-Parameter Plotter → Differential Pair Calculator → Via Inductance Calculator → Microstrip Calculator → Skin Depth & Loss → RF PCB Design → EMC & RF Interference →

Why Signal Integrity Matters

Eye Diagrams

Eye Diagram Parameters

Jitter Decomposition

Jitter Components

Jitter Budget — PCIe Gen 4 Example

ISI & Channel Loss

Skin Effect Loss

Dielectric Loss

Pre-emphasis & Equalization

TX Pre-emphasis / De-emphasis (FFE)

RX Equalization — CTLE and DFE

SerDes Architecture

Crosstalk — NEXT & FEXT

Crosstalk Worked Example

TDR Impedance Profiling

Channel Link Budget

PCIe Gen 4 (16 GT/s) Channel Link Budget

High-Speed Interface Standards

Signal Integrity in High-Speed RF and Digital Design

Impedance Matching and Reflections

Loss, Jitter and Eye Diagrams