RF Theory › EMC & RF Interference
EMC & RF Interference
A practical engineering guide to electromagnetic compatibility — emissions, immunity, shielding, filtering, grounding, common-mode noise, crosstalk, regulatory standards (FCC/CE/CISPR) and systematic EMC design for RF and mixed-signal PCBs.
01 — EMC Fundamentals
EMC Fundamentals
Electromagnetic Compatibility (EMC) requires that a device (1) does not emit interference that disrupts other equipment, and (2) is immune to interference from its environment. Every EMC problem has three elements — a source, a coupling path, and a receptor. Eliminate any one and the problem disappears.
EMC Interference Budget
Margin = Immunityreceptor(dBμV/m) − Emissionsource(dBμV/m) − Coupling(dB) > 0E-field (dBμV/m) = 20·log₁₀(E in μV/m) · E = V/m = √(P·Rrad·30)/d
0 dBμV = 1 μV referenced · 0 dBμV/m = 1 μV/m field strength
Typical ambient noise floor: −10 to +20 dBμV/m (urban, 1–1000 MHz)
The Four Coupling Paths
| Coupling Mode | Mechanism | Frequency Range | Primary Fix |
|---|---|---|---|
| Conductive | Direct wire/trace connection — shared impedance, ground loops | DC–100 MHz | Filtering, star ground, isolation |
| Capacitive | Electric field coupling between adjacent traces/components | 1 MHz–1 GHz | Physical separation, guard traces, shielding |
| Inductive | Magnetic field coupling between loops (mutual inductance) | 100 kHz–100 MHz | Reduce loop area, 90° orientation, shielding |
| Radiative | Far-field electromagnetic wave coupling | >30 MHz | Shielding, antenna separation, filtering |
The source/path/receptor framework: A 100 MHz clock radiating from a PCB trace (source) → coupling through air (path) → desensing a 100 MHz IF filter in an adjacent receiver (receptor). Fix at the cheapest point: add a ferrite bead on the clock line (source), add PCB shielding can (path), or add a bandpass filter at the IF input (receptor). In practice: fix all three.
02 — Emissions
Conducted & Radiated Emissions
Conducted Emissions (CE)
Conducted emissions are RF noise currents that flow on the power supply lines and I/O cables. They are measured using a Line Impedance Stabilisation Network (LISN) — a standardised 50 Ω impedance presented to the EUT across 150 kHz–30 MHz.
Conducted Emission Limits — FCC Part 15B Class B (Residential)
150 kHz – 500 kHz: 66 dBμV quasi-peak, 56 dBμV average500 kHz – 5 MHz: 56 dBμV quasi-peak, 46 dBμV average
5 MHz – 30 MHz: 60 dBμV quasi-peak, 50 dBμV average
Class A (commercial): limits are 10 dB higher — easier to meet
CISPR 32 Class B: similar limits, European standard (CE marking)
| CE Source | Mechanism | Frequency | Fix |
|---|---|---|---|
| SMPS switching | Drain/inductor node voltage swings | fsw harmonics: 100 kHz–10 MHz | CM choke + X/Y caps on AC input |
| Clock harmonics | Current spikes on Vdd at clock edge | Fundamental + odd harmonics | Spread-spectrum clocking, decoupling |
| I/O cable | CM current on cables acting as antennas | 30–300 MHz | CM filter at cable entry, cable ferrite |
| Microprocessor | Dynamic power supply current spikes | Broadband | Bulk + HF decoupling capacitors |
Radiated Emissions (RE)
Radiated Emission Limits — FCC Part 15B (measured at 3 m / 10 m)
30–88 MHz: Class B 100 μV/m = 40 dBμV/m at 3 m88–216 MHz: Class B 150 μV/m = 43.5 dBμV/m at 3 m
216–960 MHz: Class B 200 μV/m = 46 dBμV/m at 3 m
>960 MHz: Class B 500 μV/m = 54 dBμV/m at 3 m
Class A at 10 m: same field strength → effectively 20 dB more relaxed than Class B at 3 m
Example 1 — Estimating radiated emission from a PCB trace
100 MHz clock, 20 mA current loop, loop area A=1 cm² = 1×10⁻⁴ m², measured at d=3 m
1
Electric field from small loop: E = (2π·f)²·μ₀·I·A·sinθ / (4π·c·d) = (2π×10⁸)²×4π×10⁻⁷×0.02×10⁻⁴/(4π×3×10⁸×3)
2
E = (3.948×10¹⁷)×(8π×10⁻⁷)×(2×10⁻⁶)/(1.131×10¹⁰) = 1.75×10⁻⁴ V/m = 175 μV/m
3
In dBμV/m: 20·log₁₀(175) = 44.9 dBμV/m
4
FCC Class B limit at 88–216 MHz: 43.5 dBμV/m → we EXCEED by 1.4 dB — FAIL!
5
Fix: reduce loop area from 1 cm² to 0.5 cm² (route return path adjacent) → E drops 6 dB → 38.9 dBμV/m — PASS with 4.6 dB margin
✓ Loop area reduction is the single most effective fix. Halving loop area = 6 dB reduction. Quarter area = 12 dB. Return current routing is the EMC engineer's most powerful tool.
03 — Immunity & ESD
Immunity & ESD
Immunity testing verifies that the product survives being exposed to externally generated interference. Key tests include ESD (electrostatic discharge), EFT (electrical fast transient), surge, conducted RF immunity, and radiated RF immunity.
| Test | Standard | Level (Class 3/4) | Waveform | PCB Mitigation |
|---|---|---|---|---|
| ESD Contact | IEC 61000-4-2 | ±4 kV / ±8 kV | 0.7 ns rise, 60 ns half | TVS diodes, GDTs, chassis ground |
| ESD Air | IEC 61000-4-2 | ±8 kV / ±15 kV | 0.8 ns rise | Creepage, conformal coating |
| EFT/Burst | IEC 61000-4-4 | ±2 kV / ±4 kV | 5 ns rise, 50 ns width, 5 kHz burst | CM choke, Y-caps on I/O |
| Surge | IEC 61000-4-5 | ±2 kV / ±4 kV | 1.2/50 μs | MOV, TVS, gas discharge tube |
| Conducted RF | IEC 61000-4-6 | 3 V / 10 V EMF | 0.15–80 MHz CW/AM | CM filters, decoupling, shielding |
| Radiated RF | IEC 61000-4-3 | 3 V/m / 10 V/m | 80–1000 MHz | Shielding, filtering, layout |
ESD the most common failure mode: A human body model (HBM) ESD event discharges 100 pF at 1500 Ω → ~100 mJ in 150 ns. This can destroy gate oxides (MOS), punch through junctions, or corrupt memory. TVS diodes clamp to 5–15 V within <1 ps. Place them on every external connector pin, as close to the connector as possible — before any ESD-sensitive component.
04 — Shielding
Shielding Effectiveness
Shielding attenuates electromagnetic fields by reflection (wave impedance mismatch at the conductor surface) and absorption (energy dissipated by induced currents in the conductor). Total shielding effectiveness SE = A + R + B (absorption + reflection + multiple reflection correction).
Shielding Effectiveness
A = 131.4·t·√(f·μr·σr) (absorption loss in dB, t in metres)R = 168 − 10·log₁₀(f·μr/σr) (reflection loss — plane wave, dB, σr relative to copper)
SE = A + R + B (B ≈ 0 for A > 15 dB)
Skin depth δ = 1/√(π·f·μ·σ) mm · Copper: δ = 66.5/√f[Hz] μm · Steel: δ = 16.7/√f[Hz] μm (μr=100)
Shielding Effectiveness Examples
Example 2 — SE for 1 mm copper and 1 mm steel at 100 MHz
1
Copper δ at 100 MHz = 66.5/√(10⁸) = 6.65 μm · 1 mm = 150 skin depths → A = 131.4×0.001×√(10⁸×1×1) = 131.4 dB
2
Copper R at 100 MHz: 168−10·log₁₀(10⁸×1/1) = 168−80 = 88 dB
3
Copper SE ≈ 131.4+88 = 219 dB — solid copper is impractical to analyse — all SE is limited by apertures!
4
Steel SE at 100 MHz: A=131.4×0.001×√(10⁸×100×0.1) = 131.4×√(10⁹) = 415 dB (higher μ, lower σ)
5
Aperture-limited SE: SEaperture = 20·log₁₀(λ/2L) for aperture of max dimension L
6
10×10 mm ventilation hole at 100 MHz: λ=3 m, SE = 20·log₁₀(3/(2×0.01)) = 43.5 dB — aperture limits the whole shield!
✓ The metal wall is essentially transparent. Every aperture (seam, vent, display, connector cutout) limits SE. At 1 GHz, the same hole gives only 23.5 dB. Cover vents with wire mesh (aperture = mesh cell, not vent hole).
Seams are the weakest point: A 10 mm gap in a 1 GHz enclosure has the same SE as a 10 mm aperture — 23.5 dB. EMC gaskets (conductive foam, spring fingers, copper tape) are essential. A single seam can reduce a 100 dB shield to 20 dB. Check every seam, hinge, and removable panel with a field probe before your EMC pre-scan.
05 — EMI Filtering
EMI Filtering
EMI filters attenuate noise on power lines and I/O cables. The key distinction is between differential mode (DM) noise — current that flows line-to-line — and common mode (CM) noise — current that flows line-to-ground (or ground plane) on all conductors simultaneously.
Differential vs Common Mode
DM noise: IL = −IN (opposite on line and neutral) · Filter: X-capacitor + DM inductorCM noise: IL = IN (same direction on both) · Filter: Y-capacitors + CM choke
Insertion loss (IL) = 20·log₁₀(Vsource/Vload) with filter in circuit dB
Typically need IL > 30–50 dB at the offending frequency to pass FCC/CISPR
Common Mode Choke Design
Example 3 — CM choke for 1 MHz SMPS conducted emission fix
1
Measured CE at 1 MHz = 72 dBμV · FCC Class B limit = 56 dBμV · Need IL = 16 dB minimum, target 26 dB (10 dB margin)
2
Select Würth 744235601 CM choke: LCM=6 mH, DCR=0.36 Ω, Irated=1A
3
IL ≈ 20·log₁₀(1 + ZCM/Zsource) at 1 MHz: ZCM=2πfL=37.7 kΩ vs Zsource=50 Ω (LISN) → IL = 20·log₁₀(755) = 57.6 dB
4
Add Y-caps: 4.7 nF line-to-ground each side · ZY at 1 MHz = 1/(2π×10⁶×4.7×10⁻⁹) = 33.9 Ω
5
Combined LC filter IL increases further — predict 60+ dB, test confirms 65 dBμV → 7 dBμV = 49 dB reduction ✓
✓ CM choke + Y-caps gives 49 dB attenuation. Final CE = 72−49 = 23 dBμV — 33 dB below FCC Class B limit of 56 dBμV. Note: Y-cap is safety-limited to 4.7 nF for 50/60 Hz leakage current compliance.
06 — Grounding & Ground Planes
Grounding & Ground Planes
The ground plane is not just a 0 V reference — it is the return current path for every signal on the PCB. Signal current flows on the trace; return current flows on the ground plane directly beneath the trace (image plane effect). Interrupting the return current path forces it to detour, creating large loop areas and emissions.
| Grounding Rule | Why | Consequence if Broken |
|---|---|---|
| Solid ground plane, no splits | Return current follows signal trace above | Split → return current detours → large loop area → radiation |
| No via stitching under traces | Vias interrupt return current on plane | Ground plane becomes a slot antenna |
| Star ground for analog | Prevents ground loops at LF | Shared impedance → hum, 50/60 Hz interference |
| Single-point chassis bond at PCB | Prevents CM ground loop via chassis | Ground loop → radiated emission antenna |
| Decoupling caps at every IC Vdd pin | Reduces Vdd spike amplitude and loop area | Large current spikes → radiated emission from IC loop |
| Guard ring around sensitive analog | Returns stray capacitive currents locally | Capacitive crosstalk from digital into analog |
The 20H rule: Extend the power plane 20× the dielectric thickness inside the ground plane edges. A 1.6 mm dielectric → 32 mm power plane setback. Reduces edge-radiated fields from the power/ground plane parallel plate cavity by ~70% at frequencies where the cavity resonates. Widely used in high-speed digital PCB design.
07 — PCB EMC Design
PCB EMC Design Rules
| Area | Rule | Reason |
|---|---|---|
| Stackup | Signal / Ground / Power / Signal (4-layer minimum for EMC) | Every signal has a reference plane return path within 0.1 mm |
| Clocks | Route away from board edges and I/O connectors. Terminate with series resistor (22–33 Ω) | Board edges radiate. Series termination reduces overshoot → harmonics |
| Decoupling | 100 nF ceramic 0402 within 2 mm of each IC Vdd pin. 10 μF bulk per power rail | HF decoupling reduces di/dt voltage spike on Vdd |
| SMPS layout | Minimise hot loop area (switch node → inductor → output cap → return) | Hot loop radiates proportional to I×A×f² |
| I/O filtering | Filter all I/O at board edge — before connector pin | Cables act as antennas — filter at board edge before cable picks up |
| Crystal/oscillator | Place close to IC, guard ring, no signals crossing below | Crystal is a broadband noise source — minimise coupling length |
| RF section | Shield can around RF front end, solid ground plane, RF traces <λ/20 | RF signals radiate at any length >λ/20 — λ/20 at 2.4 GHz = 6.25 mm |
| Via stitching | Row of ground vias every λ/20 along RF traces and at shield can perimeter | Ground return path must be <λ/20 or plane becomes antenna |
08 — Regulatory Standards
Regulatory Standards
| Standard | Region | Covers | Class | Product Type |
|---|---|---|---|---|
| FCC Part 15B | USA | Unintentional radiators | A (commercial), B (residential) | PCs, TVs, embedded, IoT |
| CISPR 32 | EU/Global | Multimedia equipment emissions | A, B | Audio/video, IT equipment |
| CISPR 25 | Global | Automotive emissions | Classes 1–5 | Vehicle electronics, EV |
| IEC 61000-4-x | EU/Global | Immunity testing | Levels 1–4 | Industrial, medical, consumer |
| RED 2014/53/EU | EU | Radio equipment directive | — | Any product with radio |
| MIL-STD-461G | USA DoD | Military EMC | — | Defence electronics |
| DO-160G | Avionics | Environmental + EMC | — | Aircraft equipment |
FCC SDoC vs certification: Since 2017, most Class B devices use Supplier's Declaration of Conformity (SDoC) — self-declaration with test records held by manufacturer. Only intentional transmitters (WiFi, Bluetooth, cellular) still require FCC lab certification (ID) through an accredited test lab. SDoC does not mean no testing — you still need ANSI C63.4 measurements, just without FCC submission.
CE marking for EU market: CE marking requires a Declaration of Conformity against all applicable directives — typically LVD (low voltage), RED (radio), and RoHS. The test lab must be accredited to ISO/IEC 17025. Using a CISPR 32 compliant report as the basis for CE is the most common path for consumer electronics.
09 — EMC Debug
EMC Debug Techniques
| Technique | Equipment | Best For |
|---|---|---|
| Near-field scanning | Loop/E-field probe + spectrum analyser | Finding which trace/IC radiates most — mm spatial resolution |
| Conducted pre-scan | LISN + spectrum analyser | CE before formal test — identify offending frequencies |
| Radiated pre-scan | Biconical/log-periodic antenna + SA | RE estimate in shielded room or open area — within 6 dB of formal test |
| Current probe | RF clip-on CM current probe | Identifying which cable carries the most CM current |
| Ferrite bead test | Snap-on ferrite + SA | Rapid CE fix — confirms ferrite will work before soldering |
| Copper tape seal test | Conductive copper tape + SA | Confirm seam is the culprit — tape seals the seam temporarily |
| Time domain (TDEMI) | Wideband ADC receiver | Captures emissions vs time — identifies burst sources (SMPS, WiFi) |
The $50 fix principle: The earlier in the design cycle you address EMC, the cheaper the fix. PCB layout change at schematic review: $50. Spin a new board: $2,000. Add a shielding can after board failure: $5,000. Fail at certification, redesign, re-test: $50,000+. EMC pre-scan your own design at every board revision — before formal test lab booking.