Phase-Locked Loop (PLL) Theory — VCO, Loop Filter, Phase Noise

// Foundation

Why PLLs Exist

Every RF receiver and transmitter needs a local oscillator (LO) — a precise, stable, tunable frequency source that the mixer uses to translate signals between the RF and IF frequencies. The two requirements — precise and tunable — are fundamentally in conflict with each other in oscillator design.

A crystal oscillator is extraordinarily precise (frequency error <1 ppm) but fixed at one frequency determined by the crystal's cut. A voltage-controlled oscillator (VCO) is tunable over a wide range but imprecise and noisy on its own — its frequency drifts with temperature, supply voltage and aging.

The Phase-Locked Loop solves this by locking the output of a tunable, noisy VCO to a precise, stable crystal reference. The PLL uses feedback to continuously correct the VCO's phase and frequency, forcing it to track a divided version of the crystal frequency. The result: a tunable oscillator with the frequency precision of a crystal.

The PLL is in everything: Your smartphone uses 5–15 PLLs simultaneously — one per cellular band, one for WiFi, one for Bluetooth, one for GPS. Your WiFi router has PLLs for 2.4 GHz and 5 GHz. Your car's infotainment FM radio uses one. The GPS satellite you're connecting to uses one. Radar, 5G base stations, digital TV, satellite modems — all PLL-driven.

// System View

PLL Architecture

The Five Blocks

Every charge-pump PLL (the dominant type used in RF from 100 MHz to 100 GHz) has exactly five blocks in a feedback loop:

Reference Oscillator

TCXO / OCXO / Crystal

Provides the precision frequency reference. Usually a crystal oscillator at 10–50 MHz. Its frequency accuracy and phase noise set the floor for the entire PLL.

f_ref = 10–50 MHz typical

Phase-Frequency Detector

PFD

Compares the phase of the reference signal to the fed-back divided VCO output. Outputs an error signal: UP pulse when reference leads, DN pulse when VCO leads.

Output ∝ Δφ = φ_ref − φ_div

Charge Pump

Converts PFD UP/DN pulses into a current that charges/discharges the loop filter capacitor. Current I_cp sets the loop gain along with VCO gain K_v.

I_out = ±I_cp during UP/DN pulse

Loop Filter

LF (passive RC or active)

Converts charge pump current into VCO control voltage. Sets the loop bandwidth, phase margin, and suppresses reference spurs. The most critical design element.

H(s) = Z_LF(s) — impedance transfer function

Voltage-Controlled Oscillator

VCO

Generates the RF output frequency. Control voltage V_tune shifts the frequency. K_vco (MHz/V or rad/s/V) is the VCO gain. Dominant source of far-from-carrier phase noise.

f_out = f₀ + K_vco × V_tune

Feedback Divider

÷N (integer or fractional)

Divides the VCO output by integer N (or fractional N for frac-N PLLs) to bring it down to the reference frequency for phase comparison. Sets the output frequency.

f_out = N × f_ref (integer-N)

Complete PLL Block Diagram

The loop operates as a negative feedback system. When the VCO is running too fast (frequency too high), the divider output phase advances ahead of the reference. The PFD detects this and issues DN pulses. The charge pump reduces the control voltage. The VCO frequency drops. This continues until the two phases match exactly — at which point the PFD output is zero and the VCO holds its frequency. The VCO frequency is locked to exactly N × f_ref/R.

// Deep Dive

Each Block Explained

1. Reference Oscillator

The reference oscillator is the PLL's "ground truth" — everything the PLL produces is ultimately traceable to it. Its characteristics determine the PLL's absolute frequency accuracy and the close-in phase noise floor.

Reference Oscillator Types

Crystal (XO): ±30–100 ppm, −130 to −140 dBc/Hz at 1 kHz offset, $0.50–$2
TCXO (Temperature Compensated): ±0.5–2 ppm, −145 to −155 dBc/Hz at 1 kHz, $2–$20
OCXO (Oven Controlled): ±0.01–0.1 ppm, −160 to −170 dBc/Hz at 1 kHz, $20–$200
CSAC (Chip-Scale Atomic Clock): ±0.001 ppm, ≈−175 dBc/Hz at 1 kHz, $1500+

Leeson scaling to output: PN_out = PN_ref + 20·log₁₀(N/R)
Every factor of 10 in division ratio → +20 dB reference phase noise at PLL output

The reference frequency is typically 10–50 MHz for RF PLLs. A higher reference frequency gives wider channel spacing (or larger N for the same output), which may not be desirable. A lower reference frequency gives finer channel resolution but requires larger N — multiplying the reference phase noise by 20·log₁₀(N).

2. Phase-Frequency Detector (PFD)

The PFD is a digital state machine that compares the phase of two inputs (REF and DIV) and generates UP and DN pulse outputs. Unlike a simple XOR phase detector (which only works near 0° or 180° phase difference), the PFD works for any phase difference from −2π to +2π, including frequency differences — it can detect and correct for both phase errors AND frequency errors, allowing the loop to acquire lock even when the VCO starts far from the target frequency.

PFD Transfer Function

K_PFD = I_cp / (2π) A/rad
The PFD+CP combination converts phase error to current:
I_out = K_PFD × Δφ = (I_cp / 2π) × (φ_ref − φ_div)

Dead zone: When Δφ is very small, neither UP nor DN pulse is generated.
PFD dead zone → VCO phase noise NOT corrected by the loop → noise spike at carrier.
Modern PFDs add a small delay to eliminate dead zone.

3. Charge Pump

The charge pump converts the PFD's UP/DN current pulses into a net current that charges or discharges the loop filter capacitor. When UP is asserted, current I_cp flows into the loop filter. When DN is asserted, current I_cp is drawn from the loop filter. At lock, UP and DN pulses are equal and the net current is zero.

Charge Pump Key Parameters

I_cp: Charge pump current — typically 0.1 to 5 mA. Higher I_cp → faster loop response, wider bandwidth (for fixed loop filter).
Leakage current: Any current mismatch between UP and DN — causes a periodic correction pulse at f_ref → reference spurs.
Current mismatch ΔI: ΔI/I_cp × 6 dB per octave of mismatch → reference spur level
Phase noise contribution: PN_CP ≈ 10·log₁₀(2·k_B·T·R_n/I_cp²) + 20·log₁₀(N)

4. Loop Filter

The loop filter is the most critical design element of the PLL. It determines the loop bandwidth, phase margin, lock time, and reference spur suppression. It converts the charge pump's output current into the VCO's tuning voltage.

Loop Filter Design (Type 2, 2nd Order — Most Common)

Zero frequency: ω_z = 1/(R₁·C₁) → sets where phase boost begins
Pole frequency: ω_p2 ≈ (C₁+C₂)/(R₁·C₁·C₂) → sets where phase boost ends
Loop bandwidth (target): ω_c ≈ √(ω_z × ω_p2) — geometric mean of zero and pole
Phase margin: PM = arctan(ω_c/ω_z) − arctan(ω_c/ω_p2) → target 45–60°

Optimal component values for BW=f_c, PM=φ:
T₁ = C₁ × R₁ = tan(φ)/ω_c (time constant of zero)
C₁ = I_cp × K_vco / (N × (2π×f_c)²) × (1 + (ω_c·T₁)²)^0.5 / (ω_c·T₁)
R₁ = T₁/C₁ C₂ ≈ C₁/10 (for spur suppression, accept reduced phase margin)

5. Voltage-Controlled Oscillator (VCO)

The VCO is the only component in the PLL chain that actually generates the output RF frequency. It consists of a resonant tank circuit (LC or ring oscillator) whose resonant frequency is tunable by a varactor diode (a voltage-controlled capacitor).

VCO Key Parameters

K_vco (VCO gain): frequency change per volt — typically 10–500 MHz/V
Tuning range: frequency span with V_tune from 0 to V_supply — target ≥30% of centre freq
Free-running phase noise: Leeson's model (see Phase Noise section)
Pushing: frequency change with supply voltage — typically 1–10 MHz/V
Pulling: frequency change due to load impedance variation — significant in PA near-antenna VCOs

Relationship to loop gain:
Open-loop gain K = (I_cp × K_vco) / (2π × N)
Loop bandwidth ω_c² ≈ K × ω_z (for type-2 PLL at optimal phase margin)

6. Feedback Divider (÷N)

The feedback divider divides the VCO output frequency by N before presenting it to the PFD. This is what makes the output frequency a multiple of the reference: f_out = N × f_ref/R. Changing N changes the output frequency in steps of f_ref/R (the comparison frequency f_comp).

Divider and Frequency Resolution

Integer-N: f_out = N × f_comp where f_comp = f_ref/R
Minimum frequency step = f_comp = f_ref/R
For 200 kHz steps: f_comp = 200 kHz → N = f_out/200kHz (e.g. N=5000 for 1 GHz)

N directly affects phase noise at output:
Divider adds: PN_div_noise ≈ −224 + 20·log₁₀(N) + 10·log₁₀(f_comp) dBc/Hz

Fractional-N: f_out = (N + k/M) × f_comp
Allows non-integer division → sub-Hz frequency resolution with high f_comp
Enables wider loop bandwidth without sacrificing frequency resolution

// Control Theory

Loop Dynamics — Bandwidth, Stability & Lock Time

Open-Loop Gain

The PLL is a feedback control system. Its behaviour is analysed using control theory — specifically the open-loop gain G(s)H(s), which governs stability, bandwidth and noise transfer.

PLL Open-Loop Gain (Type 2, 2nd Order)

Forward path: G(s) = K_PFD × Z(s) × K_vco/s
where K_PFD = I_cp/(2π), Z(s) = loop filter impedance, K_vco in rad/s/V

Feedback: H(s) = 1/N

Open-loop gain: G(s)H(s) = [I_cp × K_vco × (1+sτ₁)] / [2π × N × s²(C₁+C₂)(1+sτ₂)]
τ₁ = R₁C₁ (zero time constant), τ₂ = R₁C₁C₂/(C₁+C₂) (high-frequency pole)

DC gain → ∞ (integrator — guarantees zero steady-state phase error)

Loop Bandwidth

The loop bandwidth f_c (or ω_c = 2π·f_c) is the frequency at which |G(s)H(s)| = 1 (0 dB). It is the single most important design parameter because it controls everything:

Loop Bandwidth — The Key Tradeoff

WIDER bandwidth (f_c larger):
+ Faster lock time + Better suppression of VCO phase noise + Faster frequency hopping
− Less suppression of reference spurs − Less attenuation of charge pump noise − Risk of instability

NARROWER bandwidth (f_c smaller):
+ Better reference spur suppression + Lower CP/PFD noise contribution
− Slower lock time − VCO phase noise dominates at closer offsets − Slower hopping

Rule of thumb: f_c ≤ f_comp/10 for stability (type-2 PLL)
Practical range: f_c = 1 kHz to 500 kHz for most RF PLLs

Phase Margin and Stability

A type-2 PLL (with two integrators in the forward path — the VCO and the capacitor C₁) is conditionally stable. Without the zero added by R₁, the phase of G(s)H(s) is always −180° and the loop will oscillate. The series resistor R₁ adds a zero that provides phase boost at the crossover frequency, creating positive phase margin.

Phase Margin Formula

PM = 180° + ∠G(jω_c)H(jω_c)
For type-2 PLL with one zero and one high-freq pole:
PM ≈ arctan(ω_c·τ₁) − arctan(ω_c·τ₂)

Target: PM = 45–60°
PM < 30°: Severely underdamped — large overshoot during lock acquisition, long settling time
PM = 45°: Good compromise — moderate overshoot, stable
PM = 60°: Critically damped — minimal overshoot, fastest settling to final value
PM > 70°: Overdamped — no overshoot but slower settling

Lock Time

Lock time is the time required for the PLL to settle to within a specified frequency or phase error after a frequency change. For cellular and WiFi systems, lock time determines how fast a frequency-hopping transceiver can switch channels.

Lock Time Estimation

Approximate lock time: t_lock ≈ (10 to 20) / (2π × f_c)
For f_c = 10 kHz: t_lock ≈ 160–320 μs
For f_c = 100 kHz: t_lock ≈ 16–32 μs
For f_c = 500 kHz: t_lock ≈ 3–6 μs

More precise (for second-order PLL, step Δf in frequency):
t_lock ≈ [ln(Δf/f_error_spec)] / (PM/100 × ω_c) (where PM is in degrees, ω_c = 2π·f_c)

Cellular TDMA requirement: lock in <100 μs per hop → f_c > 30 kHz minimum
Frequency synthesiser requirement: vary — some applications need <1 μs lock time

// Interactive Tool

PLL Loop Filter Calculator

Enter your PLL parameters. The calculator designs the type-2 passive loop filter (R₁, C₁, C₂), computes the loop bandwidth, phase margin, lock time, and reference spur estimate.

// Type-2 Second-Order Passive PLL Loop Filter Designer

VCO gain K_vco

MHz/V

Charge pump I_cp

Divider ratio N

Reference freq f_ref

MHz

R divider

Target loop BW f_c

kHz

Target phase margin

C₂/C₁ ratio (spur atten.)

× (C₁/C₂)

// Open-Loop Bode Plot — Magnitude and Phase

Green = magnitude (dB) · Blue = phase (°) · Red dashed = 0 dB crossover (ω_c) · Yellow dashed = −180° line

// Most Important Specification

PLL Phase Noise — Sources, Model & Shaping

Phase noise is the most critical specification of a PLL-based LO. It determines receiver sensitivity in the presence of blockers (reciprocal mixing), transmitter spectral purity (spurious emission compliance), and data rate capacity (EVM, BER in high-order modulation). Understanding where phase noise comes from and how the PLL shapes it is essential for LO design.

Phase Noise Sources in a PLL

Every active and passive component in the PLL contributes noise to the output. The PLL loop shaping function determines which components dominate at which offset frequencies:

Phase Noise Contributions at PLL Output

Reference oscillator: PN_ref(Δf) + 20·log₁₀(N/R)
Appears multiplied by N at the output — dominant at close-in offsets (<f_c)

PFD + Charge Pump: PN_CP = −174 + 10·log₁₀(I_cp) + 20·log₁₀(N·2π/I_cp) (approx)
Flat noise floor inside loop bandwidth — sets the minimum in-band noise floor

Divider ÷N: PN_div ≈ −224 + 20·log₁₀(N) + 10·log₁₀(1/f_comp) dBc/Hz
Rises 20 dB per decade increase in N — penalty for large N

VCO (Leeson's model): PN_VCO(Δf) — dominant at offsets >> f_c
Falls at 20–30 dB/decade outside loop bandwidth

Leeson's Phase Noise Model

Leeson's equation (1966) is the standard model for free-running oscillator phase noise. It describes the characteristic 1/f³ (close-in) and 1/f² (far-out) noise spectrum of an LC oscillator:

Leeson's Equation

PN(Δf) = 10·log₁₀{(2FkT/P_sig) × [1 + (f₀/2Q·Δf)²] × [1 + f_c_1f/|Δf|]}

F = noise factor of the amplifier in the oscillator (excess noise)
k = Boltzmann constant (1.38×10⁻²³ J/K), T = temperature (290 K)
P_sig = oscillator output power (Watts)
f₀ = oscillator centre frequency, Q = loaded Q of the tank circuit
Δf = offset from carrier, f_c_1f = 1/f corner frequency of the active device

The three regions:
Close-in (Δf < f_c_1f): 1/f³ slope — 30 dB/decade — flicker noise dominates
Mid-range: 1/f² slope — 20 dB/decade — white noise modulating resonator
Far-out (Δf >> f₀/2Q): flat — thermal noise floor (−174 dBm/Hz)

Key insight: Higher Q → lower PN. Every factor of 2 in Q → 6 dB lower PN.
Higher P_sig → lower PN (oscillator signal-to-noise ratio improves).

Inside vs Outside the Loop Bandwidth

The most important concept in PLL phase noise: the loop bandwidth divides the phase noise spectrum into two fundamentally different regimes.

Phase Noise Transfer Functions

Inside loop bandwidth (f_offset < f_c):
PLL phase noise tracks the reference × N + PFD/CP noise
PN_out ≈ PN_ref(Δf) + 20·log₁₀(N) + noise_floor_CP
The PLL actively corrects VCO noise in this region

Outside loop bandwidth (f_offset > f_c):
PLL cannot correct VCO noise — VCO free-runs
PN_out ≈ PN_VCO_free_running(Δf) — Leeson's model applies

Transition (f_offset ≈ f_c):
A "bump" often appears just outside f_c where VCO noise and reference noise cross
Bump height controlled by phase margin — lower PM = higher bump

Phase Noise Visualiser

VCO Q: VCO f₀ (GHz): P_sig (dBm): N (divider): Loop BW (kHz):

// Spurious Tones

Reference Spurs — Cause, Level & Suppression

Reference spurs are discrete spurious tones at the PLL output at offsets of ±f_comp (the comparison frequency = f_ref/R) and its harmonics. They appear as sharp spikes in the phase noise spectrum, distinct from the broadband noise floor.

How Reference Spurs Form

Reference spurs arise because the charge pump is never perfectly balanced. At lock, both UP and DN pulses are issued simultaneously for a very short time (reset pulse) to avoid the dead zone. Any mismatch between the UP and DN currents, or any charge pump leakage current, results in a net periodic current injection at the comparison frequency f_comp. This periodic perturbation frequency-modulates the VCO, creating FM sidebands at ±f_comp and its harmonics.

Reference Spur Level Estimation

Spur level ≈ 20·log₁₀(I_leak × K_vco / (2 × f_comp²)) dBc

I_leak = net charge pump leakage current (A)
K_vco = VCO gain (rad/s/V)
f_comp = comparison frequency (Hz)

Key relationships:
Higher f_comp → lower spur level (faster charge/discharge, smaller net error)
Higher K_vco → higher spur level (VCO more sensitive to control voltage ripple)
Better CP matching (lower I_leak) → lower spur level
Narrower loop BW → better loop filter attenuation of spur → lower spur

Spur Suppression Techniques

1. Maximise loop filter attenuation at f_comp: The loop filter acts as a lowpass filter for reference spurs. At f_comp >> f_c, the filter attenuates by approximately −40 dB/decade (type-2 filter). Place a high-frequency pole (C₂) to increase rolloff: adding C₂ = C₁/10 increases attenuation at f_comp by ~20 dB.

2. Increase the comparison frequency: Running f_comp = f_ref (no R divider, large N if needed) maximises the loop filter's rejection at the spur frequency.

3. Improve charge pump matching: Modern integrated PLL chips achieve <1% CP mismatch through careful layout. Differential CP designs with common-centroid layout help significantly.

4. Use a fractional-N PLL: Fractional-N PLLs can operate with much higher f_comp for the same output frequency step, allowing wider loop bandwidth (better VCO noise suppression) while maintaining fine frequency resolution — and the higher f_comp pushes the reference spur further from the carrier where the loop filter provides more attenuation.

5. Sub-integer frequency planning: Choose N such that f_comp is not an integer sub-multiple of any system clock — avoids coincident interference between reference spurs and system timing signals.

// Architectures

Integer-N vs Fractional-N PLL

The divider ratio N determines both the output frequency and the frequency resolution — and these two requirements are fundamentally in tension in an integer-N PLL.

Integer-N Frequency Resolution Problem

f_out = N × f_comp where f_comp = f_ref / R

Example: cellular handset, f_ref = 13 MHz, channel spacing = 200 kHz (GSM)
Require f_comp = 200 kHz → R = 13 MHz / 200 kHz = 65
For f_out = 900 MHz: N = 900 MHz / 200 kHz = 4500
Phase noise penalty: 20·log₁₀(4500) = 73 dB! above reference noise

Wider loop bandwidth needs f_c < f_comp/10 = 20 kHz → very slow lock time
This is the fundamental problem: fine channel spacing forces large N and narrow loop BW

Fractional-N Solution

f_out = (N + k/M) × f_comp (fractional division by averaging)

Same example with Frac-N: f_ref = 13 MHz, still target 200 kHz channels
Use f_comp = 13 MHz (no R divider)
For f_out = 900 MHz: N + k/M = 900/13 = 69.23 → N=69, k/M = 0.23
Phase noise penalty: 20·log₁₀(69.23) = 37 dB (36 dB better than integer-N!)
Loop BW can now be f_c < 13 MHz/10 = 1.3 MHz → very fast lock time

Fractional-N gives finer resolution, lower phase noise, AND wider loop BW simultaneously

Cost: Fractional spurs — the averaging process (sigma-delta modulator) creates quantisation noise that appears as fractional spurs and elevated in-band phase noise. Requires careful sigma-delta noise shaping.

Property	Integer-N	Fractional-N
Frequency resolution	f_comp (can't be finer)	Sub-Hz possible with large M
Comparison frequency	Must equal channel step	Can be much higher than channel step
Phase noise (in-band)	20·log₁₀(N) penalty — high N = bad	Lower N → lower penalty
Loop bandwidth	Limited by narrow f_comp	Can be much wider → faster lock
Reference spurs	At ±f_comp offsets	At ±f_comp + fractional spurs
Complexity	Simple divider	Sigma-delta modulator needed
Fractional spurs	None	Present — need careful design
Cost	Lower	Moderate premium
Used in	Fixed freq, radar LO, clock synthesis	Cellular, WiFi, SDR — any agile radio

// VCO Inside the PLL

VCO Design for PLL Applications

The VCO is the highest-frequency, most noise-critical component in the PLL. Its phase noise, tuning range, and sensitivity to supply and load directly determine the PLL's output quality. The key design tradeoffs:

LC Oscillator Tank Q

The LC tank circuit Q factor is the primary determinant of VCO phase noise. Higher Q means the tank resonates more sharply, rejecting noise over a wider frequency range around the resonant frequency. Q is limited by the inductor's series resistance at RF — metal sheet inductors on chip have Q = 5–20; off-chip printed inductors achieve Q = 30–60; off-chip bondwire or coaxial cavity resonators achieve Q = 100–1000 (cavity filters, OCXO crystals).

Tuning Range vs Phase Noise Tradeoff

A varactor diode (used for VCO tuning) adds parasitic resistance that degrades Q. A wider tuning range requires a larger varactor capacitance swing, which means more varactor loss, lower effective tank Q, and worse phase noise. This is the fundamental VCO design tradeoff: tuning range vs phase noise. Solutions include switched-capacitor banks (digital coarse tuning + analog fine tuning), multiple VCO cores covering sub-bands, and dual-loop architectures (coarse + fine).

VCO Gain K_vco — the Loop Gain Connection

VCO Gain in Loop Context

K_vco (MHz/V) must be stable over the entire tuning voltage range

Problem: varactor C-V characteristic is nonlinear → K_vco varies with V_tune
At the edges of the tuning range, K_vco drops → loop gain drops → loop bandwidth changes
Worst case: loop may become unstable if K_vco drops more than 4× from nominal value

Design rule: K_vco should vary by less than ±50% over the tuning range
If not achievable: use a gain compensation network or automatic BW adjustment in the PLL chip

// Engineering Practice

Practical PLL Design Rules

PLL Design Checklist — 10 Rules

① Choose f_comp: f_comp = f_channel_spacing for integer-N; f_comp = f_ref for fractional-N. Higher f_comp is always better (lower N, wider BW options, lower reference spurs).

② Choose loop bandwidth f_c: f_c ≤ f_comp/10 (stability constraint). Within this bound, choose f_c to minimise total integrated phase noise. Trade VCO noise (favours wide BW) against reference/CP noise (favours narrow BW).

③ Target phase margin 52°: This gives a Butterworth-like response — minimum peaking near f_c, optimal noise bandwidth. PM=45° gives a 2.4 dB phase noise bump; PM=65° is very flat but slower lock.

④ Verify loop BW variation: Recalculate f_c at K_vco_max and K_vco_min (edges of tuning range). If BW changes by more than 2×, add a gain-boosted CP or use automatic BW calibration in the PLL IC.

⑤ Reference spur budget: Estimate spur level using I_leak × K_vco / (2 × f_comp²). If too high, add C₂ to the loop filter (target C₂ = C₁/10, which moves the high-freq pole down).

⑥ Lock time check: Verify t_lock = 20/(2π·f_c) meets system requirement. If not, widen loop BW (increase f_c) or use a lock-assist mechanism (frequency presetting the VCO).

⑦ Phase noise budget: Compute in-band floor (CP+PFD noise × N), VCO noise at offset, and total integrated phase noise from 10 Hz to 10 MHz. Verify against system requirement (e.g. −140 dBc/Hz at 1 MHz offset for LTE LO).

⑧ Supply decoupling: VCO supply and CP supply must be decoupled with <10 Ω impedance at f_comp. Use 10 nF + 100 nF in parallel, placed within 2 mm of the IC. Poor decoupling raises reference spurs and pushes VCO frequency.

⑨ Loop filter component tolerances: C₁ and R₁ should be ±1% or better (5% causes f_c variation of 5%, PM variation of 3°). Use 1% resistors and C0G/NP0 capacitors for C₁ (not X7R — X7R capacitance varies ±15% with voltage).

⑩ Layout: Keep loop filter physically close to the PLL chip. Route the VCO control voltage trace with a ground shield. Separate analog ground from digital ground, joining at one point near the PLL.

// Complete Design

Worked Example — 2.4 GHz WiFi LO Synthesiser

Design Specification — 2.4 GHz WiFi LO

Target output: 2400–2484 MHz (WiFi 2.4 GHz band, 13 channels at 5 MHz spacing)
Reference: 26 MHz TCXO (available on phone PCB, ±1 ppm)
Channel step: 5 MHz
Phase noise requirement: <−130 dBc/Hz at 1 MHz offset
Lock time: <100 μs
Reference spur: <−60 dBc

Frequency plan — Integer-N or Fractional-N?
Integer-N with f_comp = 5 MHz: R = 26/5 = 5.2 → not integer → can't do exactly 5 MHz with integer R
Try f_comp = 2 MHz: R = 13 → N = 2400/2 = 1200. Phase noise penalty = 20·log₁₀(1200) = 61.6 dB.
Use Fractional-N: f_comp = 26 MHz (R=1), N ≈ 92.3 for 2400 MHz. Penalty = 20·log₁₀(92.3) = 39.3 dB. Far better!

VCO selection:
Need 2400–2484 MHz, K_vco ≈ 50 MHz/V, Q ≈ 12 (on-chip CMOS LC VCO typical)
Leeson's model: P_sig = 0 dBm, F = 5 dB → PN_VCO(1 MHz) ≈ −120 dBc/Hz (free-running)

Choose loop bandwidth:
Lock time <100 μs: f_c > 20/(2π × 100μs) = 32 kHz minimum
VCO noise dominates above f_c; reference noise dominates inside. Optimum: f_c ≈ 100–200 kHz
f_comp = 26 MHz → f_c constraint: f_c < 26/10 = 2.6 MHz. Choose f_c = 200 kHz

Loop filter design (PM = 52°, f_c = 200 kHz):
I_cp = 1 mA, K_vco = 50 MHz/V = 2π × 50×10⁶ rad/s/V, N ≈ 92
Loop gain K = I_cp × K_vco / (2π × N) = 0.001 × 2π×50×10⁶ / (2π × 92) = 543 krad/s²
ω_c = 2π × 200 kHz = 1.257 Mrad/s
τ₁ = tan(52°) / ω_c = 1.28 / 1.257×10⁶ = 1.018 μs
C₁ = K / (N × ω_c²) × correction ≈ 1.8 nF
R₁ = τ₁/C₁ = 1.018μs / 1.8nF = 566 Ω → use 560 Ω
C₂ = C₁/10 = 180 pF

Phase noise at 1 MHz offset:
In-band floor (CP dominated): ≈ −150 dBc/Hz + 39 dB = −111 dBc/Hz (estimated, depends on CP quality)
VCO at 1 MHz offset (>> f_c=200 kHz): PN_VCO ≈ −120 dBc/Hz (free-running VCO)
Total ≈ −120 dBc/Hz dominated by VCO outside loop BW ✓ meets −130 dBc/Hz spec
(Actual measurement typically shows −125 to −135 dBc/Hz at 1 MHz for modern CMOS PLL)

Reference spur:
Filter attenuation at f_comp = 26 MHz >> f_c = 200 kHz: > 60 dB suppression
Typical CP leakage I_leak = 10 nA: spur ≈ 20·log₁₀(10nA × 2π×50×10⁶ / (2 × 26×10⁶²)) ≈ −75 dBc ✓

Result: C₁=1.8 nF, R₁=560 Ω, C₂=180 pF · Loop BW=200 kHz · PM≈52° · Lock time≈16 μs · PN≈−120 dBc/Hz at 1 MHz

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