RF PCB Design & Signal Integrity — Stackup, Return Currents, Crosstalk, EMI

// Foundation

Why PCB Signal Integrity Matters

At low frequencies, a wire is a wire — it simply connects two points. As frequency rises, the wire becomes a transmission line: its geometry (width, height above a reference plane, dielectric constant) determines its characteristic impedance Z₀, and any impedance discontinuity reflects signal energy back toward the source. By 1 GHz, a 3 cm trace is λ/10 — long enough for reflections to corrupt a digital eye or raise an RF noise floor by 10–20 dB.

Signal integrity (SI) is the discipline of ensuring that signals arrive at their destination with sufficient amplitude, timing accuracy, and spectral purity. For RF designs, SI overlaps with electromagnetic compatibility (EMC): the same physical mechanisms that degrade signal quality also cause unwanted emissions and susceptibility to interference.

The three SI killers in RF PCB design: (1) Impedance discontinuities — reflections at every Z₀ mismatch. (2) Poor return current paths — current forced to detour creates a loop antenna. (3) Crosstalk — capacitive and inductive coupling between adjacent traces injects noise into victims. All three get worse with frequency squared or faster.

// Board Architecture

Layer Stackup

Microstrip vs Stripline

The two fundamental transmission line structures on a PCB are microstrip (trace on an outer layer, reference plane below) and stripline (trace buried between two reference planes). The choice between them is the first and most important stackup decision.

Microstrip

Trace on outer layer, one reference plane below (distance h).

Z₀ ≈ (87/√(εr+1.41)) · ln(5.98h/(0.8w+t))

Pros: Easy inspection and rework. Lower capacitance → higher speed for same width. No via stubs when routing between layers.
Cons: Higher radiation — field partly in air. More crosstalk (fields less confined). Sensitive to solder mask permittivity. Not suitable for very high-frequency RF (>6 GHz) without controlled dielectric.

Stripline

Trace buried between two reference planes (distance b = h1+h2).

Z₀ ≈ (60/√εr) · ln(4b/(0.67π(0.8w+t)))

Pros: Fields fully confined between planes → much lower radiation and crosstalk. Pure TEM mode → no dispersion. Better phase noise isolation.
Cons: No rework access. Vias required for every layer change. Tighter width tolerances needed. Via stubs are a problem at high frequency.

GCPW (Grounded CPW)

Trace with ground coplanar gaps on same layer + ground plane below.

Z₀ depends on w, gap g, h, εr — requires Conformal Mapping or field solver

Pros: Easy component attachment. Dominant mode at mmWave (GCPW preferred over microstrip above 30 GHz). Tight field confinement with ground stitching vias.
Cons: Coplanar grounds must be stitched with vias every λ/20. Width + gap both must be controlled.

Embedded Microstrip

Microstrip covered by a dielectric layer (e.g. prepreg, solder mask thick).

εeff_covered ≈ εr · (1 − exp(−1.55t_cover/h))

Used for: Reducing radiation on inner microstrip layers. Effective permittivity increases → trace must be slightly narrower for the same Z₀. Commonly the default in modern multilayer PCBs.

Dielectric Materials

Common PCB Dielectrics

FR4 (standard): εr = 4.0–4.8 (varies with glass weave, frequency, moisture), tanδ = 0.015–0.025
At 10 GHz: tanδ ≈ 0.025 → insertion loss ≈ 1.5 dB/cm. Not suitable above 5 GHz for RF.

Rogers 4003C: εr = 3.55 ±0.05, tanδ = 0.0027 at 10 GHz. Low variation with frequency.
At 10 GHz: insertion loss ≈ 0.25 dB/cm. Standard for RF/microwave PCBs up to 30 GHz.

Rogers 4350B: εr = 3.66, tanδ = 0.0037. Slightly higher loss than 4003C but UL-certified for flame retardance. Very common in production RF boards.

PTFE / Rogers RT/duroid: εr = 2.2–2.94, tanδ = 0.0009–0.002. Lowest loss. Used above 30 GHz, in mmWave radar, satellite LNBs. Very soft — fragile, expensive.

Megtron 6 / Panasonic M6: εr = 3.7, tanδ = 0.002 at 10 GHz. Low-loss organic laminate. Cost between FR4 and Rogers. Used in 5G base station PCBs, high-speed backplanes.

Insertion loss from dielectric: α_d = 27.3·(εr/(εr−1))·(εeff−1/√εeff)·tanδ·f/c dB/m

Common Stackup Examples

// Controlled Impedance

Trace Impedance Control

Z₀ Formulas for Common Structures

Microstrip — IPC-2141A Approximation

Z₀ = (87/√(εr+1.41)) · ln(5.98h / (0.8w + t))
h = dielectric height (trace to reference plane), w = trace width, t = trace thickness
Valid for: 0.1 < w/h < 2.0 and 1 < εr < 15

Effective permittivity: εeff = (εr+1)/2 + (εr−1)/2 · (1+12h/w)^−0.5
Phase velocity: v_p = c/√εeff
Wavelength on board: λ = λ₀/√εeff (shorter than free-space wavelength!)

Stripline — Centered Trace (IPC-2141A)

Z₀ = (60/√εr) · ln(4b / (0.67π(0.8w+t)))
b = total dielectric thickness between reference planes, w = trace width, t = trace thickness
Valid for: w/b < 0.35 and t/b < 0.25

Off-center stripline (offset by d from one plane):
Uses two effective b values: b1 = d, b2 = b−d. Coupled to nearer plane more strongly.

Differential Pair Impedances

Odd-mode impedance: Z_odd = Z₀ · (1 − 0.347·exp(−2.9s/h)) (microstrip, IPC approx)
Differential impedance: Z_diff = 2 · Z_odd
Even-mode impedance: Z_even = Z₀ · (1 + 0.347·exp(−2.9s/h))
Common-mode impedance: Z_cm = Z_even/2
s = edge-to-edge spacing between traces

Rule of thumb: for s > 3×h, coupling is negligible and Z_diff ≈ 2×Z₀(single)
Typical target: Z_diff = 100 Ω (USB, PCIe, LVDS) or 85 Ω (DDR, some RF)

Manufacturing Tolerances

Even with a perfect design, the fabricated board deviates from the target impedance due to manufacturing variations. Understanding these tolerances is critical for RF designs where a ±10% Z₀ variation causes a measurable return loss.

Typical PCB Impedance Tolerances

Standard PCB fab: ±10% impedance tolerance — acceptable for <3 GHz digital signals
Controlled impedance fab: ±5% impedance tolerance — most RF designs
High-precision: ±2% impedance tolerance — requires premium laminate, tight etch control

Sources of variation:
Trace width ±12μm (etch undercut) → ±3–5% Z₀ change
Dielectric height ±10% (prepreg compression variability) → ±5–8% Z₀ change
εr variation ±0.1–0.5 (material lot variation, moisture) → ±2–5% Z₀ change
Trace thickness ±5μm (plating variation) → ±1–2% Z₀ change

Return loss from mismatch: RL = 20·log₁₀((Z_actual−Z_ref)/(Z_actual+Z_ref))
For ±5% mismatch (52.5 Ω vs 50 Ω): RL = 20·log₁₀(2.5/102.5) = −32 dB — acceptable
For ±10% mismatch (55 Ω vs 50 Ω): RL = 20·log₁₀(5/105) = −26 dB — marginal for RF

// The Most Misunderstood Concept

Return Current Paths

Why Return Currents Follow the Signal

This is the single most important and most misunderstood concept in PCB signal integrity. When a signal propagates along a trace, it does not return through a random path — it returns through the path of minimum impedance, which at high frequencies is the path of minimum inductance, which is directly beneath the signal trace on the reference plane.

The return current is not travelling the same direction as the signal — it travels in the opposite direction, directly beneath the trace, as a mirror image. The signal and its return current form a transmission line pair whose geometry (trace-to-plane distance) determines Z₀. At DC and low frequencies, return current spreads over the entire ground plane by resistance. Above the transition frequency f_t = R/(2πL) ≈ a few kHz for typical traces, inductance dominates and the current concentrates beneath the signal trace.

Reference Plane Splits and Gaps

Any gap, slot, or split in the reference plane forces return current to detour around it. This creates a large current loop which acts as a loop antenna — both radiating EMI and inductively coupling onto adjacent traces. Even a small slot from a connector cutout or power/ground plane split can cause 10–20 dB of EMI increase and significant impedance discontinuity on crossing traces.

Golden rule: Never route a high-speed or RF trace across a gap, slot, split, or cutout in the reference plane. If unavoidable, bridge the gap with a stitching capacitor (typically 100 nF) as close to the trace crossing as possible, providing a low-impedance return path at the crossing frequency.

Layer Transitions — Via Return Path

When a signal transitions from one layer to another via a via, the return current must also transition. If the return current's reference plane changes (e.g. signal on L1 referenced to L2-GND, transitions to L3 referenced to L4-GND), the return current must jump between the two GND planes. Without a nearby GND stitching via, the return current travels a long path on the plane — again creating a large loop and EMI.

Via Inductance (return path stub)

L_via ≈ 5.08 · h · [ln(4h/d) + 1] nH (h in mm, d = via barrel diameter in mm)
A 1.6 mm board with 0.3 mm via: L_via ≈ 5.08×1.6×(ln(4×1.6/0.3)+1) ≈ 1.2 nH
Impedance at 1 GHz: jωL = j2π×10⁹×1.2×10⁻⁹ = j7.5 Ω — significant!

Rule: Place GND return vias within 500 μm of every signal via. For differential pairs, return vias on each side of the pair. For layer transitions above 5 GHz, via spacing ≤λ/20 on the board.

// High-Frequency via behaviour

Via Stubs & Resonances

Via Stub Resonance Frequency

When a via connects a signal from an outer layer to an inner layer, the unused portion of the via barrel below the signal connection point is called the via stub. This stub acts as an open-circuited transmission line section. At the frequency where the stub length is λ/4, it presents a short circuit at the signal connection point — creating a notch (null) in the insertion loss that can be 20–40 dB deep.

Via Stub Resonance

f_stub = c / (4 · L_stub · √εr_eff)
L_stub = stub length (distance from signal connection point to bottom of via barrel)
εr_eff ≈ εr_substrate (typically 4.0–4.5 for FR4)

Example: 6-layer board, signal enters at L3, via drills all the way to L6
Stub = bottom of via from L3 to L6 ≈ 0.8 mm
f_stub = 3×10⁹ / (4 × 0.8×10⁻³ × √4.2) = 14.5 GHz — notch at 14.5 GHz
If you need >10 GHz signal bandwidth, this stub kills your signal.

Rule of thumb: f_stub > 3 × f_signal to avoid significant degradation
For 10 Gbps SerDes (≈5 GHz 3rd harmonic): f_stub > 15 GHz → L_stub < 0.8 mm → backdrilling needed

Backdrilling (Controlled-Depth Drilling)

Backdrilling (also called controlled-depth drilling or back-boring) removes via stubs by drilling from the backside of the board to a controlled depth, cutting off the unused barrel below the signal connection. The remaining stub after backdrilling is typically 50–100 μm, pushing the stub resonance above 100 GHz.

Backdrilling Impact

Without backdrilling: f_stub ≈ 14 GHz for a typical 1.6 mm board (L1→L3 signal)
With backdrilling to 100 μm stub: f_stub = c/(4×0.1×10⁻³×√4.2) ≈ 365 GHz — no issue to 100 GHz

Backdrilling adds cost ($0.10–0.50 per via) and requires tight depth control (±50 μm).
Alternative: use blind/buried vias (more expensive, fewer fab vendors).
Alternative: route all signals on outer layers only (simpler at low layer count).

// Trace-to-Trace Coupling

Crosstalk — NEXT, FEXT & 3W Rule

Near-End and Far-End Crosstalk

Crosstalk is the unwanted coupling of a signal from one trace (aggressor) to an adjacent trace (victim). It has two fundamentally different components arising from the inductive (magnetic field) and capacitive (electric field) coupling between the traces.

NEXT (Near-End CrossTalk): Crosstalk measured at the same end as the aggressor source. Inductive and capacitive coupling components add in the backward direction. For microstrip, NEXT grows linearly with coupled length up to λ/4, then saturates. For stripline, NEXT = 0 if the structure is symmetric (capacitive and inductive coefficients exactly cancel) — this is why stripline has naturally lower crosstalk than microstrip.

FEXT (Far-End CrossTalk): Crosstalk at the far end of the victim (opposite end from aggressor source). Inductive and capacitive components partially cancel. FEXT ∝ (coupled length)² / (rise time)² — grows with length squared, very bad for long parallel runs.

Crosstalk Quantified

Crosstalk Coefficients (Microstrip)

Backward crosstalk coefficient: K_b = (1/4) · (C_m/C_L − L_m/L_L)
C_m = mutual capacitance per unit length, C_L = self capacitance per unit length
L_m = mutual inductance per unit length, L_L = self inductance per unit length

NEXT voltage (saturated, for T_D > T_r/2): V_NEXT = K_b · V_sw
V_sw = signal swing voltage

FEXT coefficient: K_f = (T_D/T_r) · (C_m/C_L + L_m/L_L) / 2
T_D = one-way delay of coupled length, T_r = signal rise time
FEXT voltage: V_FEXT = K_f · V_sw

Capacitive coupling: C_m ≅ ε₀εr · w / (π · s) (s = edge-to-edge spacing >> h)
Inductive coupling: L_m ≅ (μ₀/2π) · ln(1 + w²/s²) (simplified)

Coupling vs Spacing (Practical Rules)

Coupling attenuation ≅ 20·log₁₀(s/h) — increases 20 dB per decade of s/h ratio

s/h = 1: coupling ≈ −15 dB (very high — avoid for RF)
s/h = 2: coupling ≈ −21 dB (high)
s/h = 3: coupling ≈ −25 dB (3W rule, typical minimum)
s/h = 5: coupling ≈ −30 dB (good)
s/h = 10: coupling ≈ −40 dB (excellent — use for RF isolation)

Note: s/h here uses edge-to-edge trace spacing. For 50 Ω microstrip at h=100 μm: w≈185 μm. 3W rule → edge spacing ≥ 2×185 = 370 μm.

The 3W Rule and Guard Traces

The 3W rule states that the centre-to-centre spacing between adjacent traces should be at least 3 times the trace width W to achieve approximately −25 dB of crosstalk reduction. This means edge-to-edge spacing ≥ 2W (since centre-to-centre = W + edge-to-edge).

For RF lines requiring more isolation (e.g. TX and RX in an FDD radio, or an LO trace near an IF trace), a guard trace with periodic ground stitching vias can provide an additional 10–15 dB of isolation. The guard trace must be grounded at both ends and with via stitching at least every λ/10 to be effective. An ungrounded guard trace actually increases crosstalk by resonating!

// Differential Signalling

Differential Pairs — Routing & Skew

Differential Impedance and Coupling

Differential signalling sends the same data on two traces with opposite polarity. The receiver responds only to the voltage difference, rejecting any common-mode noise (supply noise, ground bounce, EMI) that appears identically on both traces. This common-mode rejection ratio (CMRR) can be 40–80 dB, making differential interfaces far more immune to PCB noise than single-ended signals.

The key parameter is the differential impedance Z_diff — what a differential driver sees looking into the pair. Z_diff depends on both the single-ended impedance Z₀ of each trace and the coupling between them. For loosely coupled pairs (s > 3h), Z_diff ≈ 2×Z₀. For tightly coupled pairs (s < h), Z_diff is significantly lower due to strong mutual capacitance.

Differential and Common-Mode Impedance

Loosely coupled (s > 3h): Z_diff ≈ 2 · Z₀ (no coupling correction needed)
Tightly coupled (s ≈ h): Z_diff = 2 · Z₀ · (1 − K) where K = coupling coefficient

Common-mode impedance: Z_cm = Z₀/2 · (1 + K)
For Z_diff = 100 Ω target: Z₀ must be 50 Ω if uncoupled, but slightly higher (>50 Ω) if the pair is tightly coupled (coupling reduces Z_diff below 2×Z₀).

USB 3 SuperSpeed: Z_diff = 90 Ω ±7%
PCIe Gen 4/5: Z_diff = 85 Ω ±5%
LVDS: Z_diff = 100 Ω ±10%
DDR4 clock: Z_diff = 100 Ω ±10%

Skew and Length Matching

Skew is the difference in propagation delay between the two traces of a differential pair. It converts differential signal to common-mode noise at a rate of approximately 1% skew → 1% mode conversion (i.e. −40 dB differential-to-common-mode rejection degrades by the skew fraction). For high-speed interfaces, skew must be controlled to a fraction of the unit interval (UI = 1/bit_rate).

Skew Requirements

Propagation delay: t_pd = √εeff / c ≈ 70–85 ps/cm (for εr=4.2)
Length mismatch ΔL causing skew Δt = ΔL · t_pd

USB 3.1 Gen 2 (10 Gbps): max skew = 15 ps → ΔL ≤ 0.2 mm
PCIe Gen 5 (32 GT/s): max intra-pair skew = 5 ps → ΔL ≤ 0.06 mm
DDR4-3200: max skew ≈ 5 ps → ΔL ≤ 0.07 mm

Length matching methods: Serpentine (accordion) meanders on the shorter trace. Keep meander amplitude < 3×h to avoid coupling between legs. Match lengths to within spec within the same reference plane region.

// PDN — Power Delivery Network

Power Planes & Decoupling

Plane Resonance (Parallel Plate Resonator)

A power-ground plane pair forms a parallel-plate transmission line. Like any resonant structure, it has a set of resonant frequencies at which the impedance between the planes spikes. At these resonant frequencies, transient currents drawn by ICs create large voltage fluctuations on the supply — this is called simultaneous switching noise (SSN) or delta-I noise.

Plane Resonant Frequencies

f_mn = (c / (2√εr)) · √((m/a)² + (n/b)²)
m, n = mode indices (1,0 and 0,1 are lowest modes), a = board length, b = board width

Lowest resonance example: a=200mm, b=150mm, εr=4.2
f_10 = (3×10⁹/(2×√4.2)) · (1/0.2) = 366 MHz
f_01 = (3×10⁹/(2×√4.2)) · (1/0.15) = 488 MHz
These resonances can cause 100–300 mV supply ripple on lightly decoupled boards

Mitigation: Thin dielectric between power and ground planes (tight coupling = high capacitance per area, lower plane impedance). Embedded capacitance laminate (ECL): εr=10, h=50μm → 3 nF/cm² between planes.

Decoupling Capacitor Placement and Effectiveness

Decoupling capacitors act as local charge reservoirs. When an IC demands a burst of current faster than the power supply can respond, the decoupling capacitor supplies the instantaneous charge. Their effectiveness depends critically on placement — the loop inductance between the capacitor and IC must be minimised.

Decoupling Capacitor Rules

Self-resonant frequency: f_SRF = 1/(2π√(LC_parasitic))
Below f_SRF: capacitor behaves as a capacitor (good decoupling)
Above f_SRF: capacitor behaves as an inductor (poor decoupling — use smaller cap)

Typical f_SRF: 0402 100nF ≈ 10–30 MHz, 0402 10nF ≈ 50–100 MHz, 0402 1nF ≈ 200–500 MHz
Use parallel capacitors: 100nF + 10nF + 1nF covers 1 MHz – 1 GHz

Mount inductance L_mount ≈ 0.3–1.5 nH per via/pad combo
Use 2 vias per pad (parallel inductance ÷2). Use vias in pad for BGAs.
Place capacitors ≤2mm from IC power pin — each mm adds ≈0.8 nH mount inductance.

Effective decoupling radius: r_eff ≈ t_rise · c / (2√εr)
For t_rise = 100 ps: r_eff = 100×10⁻¹² × 3×10⁹ / (2×2.05) = 7.3 mm
Capacitors beyond r_eff arrive too late and do not help that switching edge.

// Electromagnetic Compatibility

EMI Control & Shielding

Slot and Aperture Resonances

Any opening (slot, gap, hole, connector cutout) in a metal enclosure or ground plane can act as a slot antenna. A slot of half-wavelength resonates strongly, radiating like a dipole. For EMC compliance, all apertures must be smaller than λ/20 at the highest frequency of concern.

Slot Resonance and EMC Aperture Rule

Slot resonant frequency: f_res = c / (2 · L_slot)
A 30 mm slot resonates at f_res = 3×10⁹/(2×0.03) = 5 GHz — a serious 5 GHz EMI source
A 150 mm slot (e.g. a long PCB edge connector gap): f_res = 1 GHz

Aperture attenuation (shielding effectiveness of an opening):
SE_aperture = 20·log₁₀(λ/(2·L_slot)) dB when L_slot < λ/2
A 5 mm slot at 3 GHz (λ=100mm): SE = 20·log₁₀(100/(2×5)) = 20 dB
A 1 mm slot at 3 GHz: SE = 20·log₁₀(100/2) = 34 dB

Rule: Maximum aperture dimension < λ/20 at the highest frequency of concern for >26 dB shielding

Shielding Effectiveness

Metal Shield — Reflection, Absorption, Re-reflection

Total SE = SE_R + SE_A + SE_B
SE_R = reflection loss (impedance mismatch at air-metal boundary)
SE_A = absorption loss (skin effect — field attenuates as e^(−t/δ) through thickness t)
SE_B = re-reflection correction (negative, usually <2 dB, often neglected)

Reflection: SE_R ≈ 20·log₁₀(σ/(16π·f·μ)) (σ = conductivity, μ = permeability)
Copper at 1 GHz: SE_R ≈ 154 dB. Aluminium: 149 dB. Steel (μr=100): 134 dB.

Absorption: SE_A = 8.686 · t/δ (δ = skin depth)
Skin depth δ = √(2/(ωμσ)): copper at 1 GHz: δ = 2.1 μm
1 mm copper at 1 GHz: SE_A = 8.686 × 1000/2.1 ≈ 4140 dB! — absorption dominates
Even 0.05 mm (50 μm) copper: SE_A = 207 dB at 1 GHz — more than sufficient

Bottom line: metal thickness is NOT the limiting factor. Apertures and seams are.
A perfect 1 mm copper box with one 15 mm slot has SE limited to ≈20 dB at 10 GHz — not 4000 dB.

EMC design is dominated by apertures, not material thickness. A 1 mm thick steel enclosure with a 10 cm cable connector opening is not a shield — it is a horn antenna. Every opening, every cable, every unsealed seam must be treated as a potential EMI source or entry point.

// PCB Trace Impedance & Crosstalk Calculator

Structure type

Trace width w

μm

Dielectric height h

μm

Trace thickness t

μm

Dielectric constant εr

Edge-to-edge spacing s

μm

Loss tangent tanδ

Frequency

GHz

// Coupling vs Trace Spacing (for current parameters)

Red dashed = current spacing · Green zone = <−30 dB coupling · Yellow = <−20 dB · Red zone = >−20 dB (high coupling)

// Engineering Practice

RF PCB Design Rules — 15 Rules

Stackup & Layer Assignment

① Every signal layer must have an adjacent reference plane: No floating layers between two signal layers without a ground/power plane. RF traces on L3 must have GND on L2 AND L4.

② Separate RF and digital power planes: RF analogue ground and digital ground as separate copper pours, joined at one star point near the DC supply. Prevent digital switching currents from flowing in the RF ground return path.

③ Use stripline for RF traces above 3 GHz: Fields confined between planes → lower radiation and crosstalk. Accept the routing complexity — the SI improvement is worth it above 3 GHz.

④ Via stub management: For signals above 5 GHz, use blind vias or specify backdrilling on all vias where stub length >1 mm. Target f_stub > 3×f_signal.

Return Currents & Plane Continuity

⑤ Never cross plane splits with RF or high-speed signals: Route around splits. If unavoidable, bridge with a 100 nF stitching capacitor across the split directly at the trace crossing.

⑥ Place return vias within 500 μm of every signal via: For every layer transition, the return current needs a local path. One GND via per signal via is minimum; for differential pairs, one GND via on each side.

⑦ Stitch ground planes with vias every λ/10: For RF boards above 1 GHz, ground pour regions need periodic via stitching. λ/10 at 10 GHz = 5 mm in FR4. Without stitching, the ground pour resonates and becomes an EMI antenna.

Trace Routing

⑧ Control trace impedance to ±5%: Specify as a fab note: "Controlled impedance: 50Ω ±5% on L1 traces marked [Z50]". Use 1:1 width:spacing ratio for 50Ω in most stackups.

⑨ Apply 3W rule for RF traces: Centre-to-centre spacing ≥ 3×W. For TX and RX paths in the same board, space by 10W or use a stripline layer with a ground layer between TX and RX.

⑩ Keep RF traces short and direct: Every 1 cm of 50 Ω microstrip adds ≈0.06 dB insertion loss at 5 GHz (FR4). Every bend should be chamfered (45°) or radiused — right-angle bends create impedance discontinuities of ≈−25 dB return loss at high frequency.

⑪ Differential pair rules: Keep intra-pair spacing constant. Avoid vias in the middle of a pair (impedance discontinuity). Match lengths to <0.1 mm within a pair. Route both traces with the same layer-change via pattern.

Power Delivery & Decoupling

⑫ Thin power-ground dielectric: Target <100 μm between power and ground planes for embedded decoupling. Use 3313 or 2116 prepreg (80–100 μm) rather than core material (200+ μm) between PWR and GND planes.

⑬ Three-tier decoupling: Bulk (10–100 μF electrolytic near connector), mid-range (100 nF 0402 on every supply pin), high-frequency (10 nF or 1 nF 0201/0402 within 1 mm of IC). Parallel values target different frequency decades.

⑭ Minimize via inductance for decoupling caps: Two vias per pad for decoupling capacitors. Vias-in-pad for 0201 components on high-frequency supply rails. Each via contributes 0.3–0.5 nH — parallel vias halve this.

EMI Control

⑮ Aperture control: Any opening in a shield or ground plane <λ/20 at the highest frequency. For 10 GHz (λ=15 mm in free space): max aperture = 0.75 mm. Use gasketed seams for enclosures above 1 GHz.

⑯ Cable management: Every cable exit is a potential antenna. Add common-mode chokes at all cable/connector exits for digital signals leaving the board. Use shielded cables and connect shield at both ends for RF.

// Complete Design

Worked Example — 5 GHz WiFi RF Front-End PCB

Design Specification

Application: 5 GHz WiFi RF front-end, TX/RX on same board, RFIC to antenna connector
Frequency: 5.15–5.85 GHz (700 MHz bandwidth)
Material: Rogers 4350B (εr = 3.66, tanδ = 0.0037) for RF layers, FR4 core for digital
Target: ≤0.5 dB insertion loss per 25 mm RF trace, ≤−40 dB TX/RX isolation on board

Stackup selection:
Use 6-layer mixed substrate: Rogers 4350B prepreg on L1/L2 (RF section), FR4 core for L3–L6 (digital)
RF traces on L1 (microstrip), referenced to L2 GND. Target h = 127 μm (5 mil Rogers 4350B prepreg)
Digital signals on L5/L6, referenced to L4 GND, isolated from RF by L2 and L3 copper pours.

50 Ω trace width on Rogers 4350B:
Using microstrip formula: Z₀ = (87/√(3.66+1.41)) · ln(5.98×127/(0.8w+35))
Solve for w: iteratively → w = 280 μm gives Z₀ ≈ 49.8 Ω ↔ spec ±1%
εeff = (3.66+1)/2 + (3.66−1)/2 · (1+12×127/280)^−0.5 = 2.87
Phase velocity = c/√2.87 = 1.77×10⁹ m/s λ at 5.5 GHz = 32 mm on board

Insertion loss budget (25 mm trace):
Dielectric loss: α_d = 27.3×(3.66/2.66)×(1.87/√2.87)×0.0037×5.5×10⁹/(3×10⁹) ×25mm ≈ 0.18 dB
Conductor loss (copper roughness ∂α_c): at 5 GHz ≈ 0.15 dB for 25 mm
Total trace loss ≈ 0.33 dB ✓ within 0.5 dB budget

TX/RX isolation:
TX trace on L1 north side, RX trace on L1 south side. Separation = 10 mm
s/h = 10mm/0.127mm = 79. Coupling = −20·log(79) ≈ −38 dB at low frequency
At 5.5 GHz, add stripline guard on L2 between TX and RX copper pours.
With guard: estimated TX/RX isolation = −55 dB ✓ meets spec

Via stub check (RFIC to L1 via):
RFIC BGA on L1, signal enters via to connector on L1 (no layer change needed ✓)
However, GND vias for L2 plane: full-board depth = 1.2 mm → f_stub = 3×10⁹/(4×1.2×10⁻³×√3.66) = 32 GHz ✓

Decoupling (RFIC supply at 3.3 V):
Place 100 nF 0402 within 1.5 mm of RFIC supply pin (f_SRF ≈ 20 MHz)
Place 10 nF 0402 within 0.5 mm (f_SRF ≈ 80 MHz)
Place 1 nF 0201 in-pad if available (f_SRF ≈ 400 MHz)
Covers decoupling from 10 MHz to 1 GHz — RFIC internal bypass handles >1 GHz

⚡ Microstrip Calculator → ⚡ Stripline Calculator → ⚡ Diff Pair Calculator → ⚡ Via Inductance Calculator → ⚡ Skin Depth Calculator → ⚡ GD, TDR & SI Analyser → 📚 Transmission Line Theory → 📚 S-Parameter Theory →