RF Theory › PA Design
RF PA Design
A practical engineering guide to designing RF power amplifiers — from device selection and load-line analysis through output matching network synthesis, bias circuit design, stability analysis, thermal management and PCB layout. Worked examples for a 2.4 GHz WiFi PA and 3.5 GHz 5G NR PA.
01 — Where to Start
PA Design Flow
PA design is iterative and heavily measurement-driven. The flow below is the industry standard sequence — skip any step and you'll spend twice as long debugging.
01
Specify requirements: Frequency, bandwidth, Pout, PAE, linearity (ACPR/EVM), supply voltage, package/size constraints. Write these down before touching a transistor.
02
Select transistor: GaN for high power/efficiency. GaAs for handset/low voltage. LDMOS for <6 GHz base station. Use device datasheet load-pull data to confirm the device can meet your Pout + PAE spec simultaneously.
03
Load-line analysis: Determine the optimum output impedance R_opt from the device I-V curves. This is the starting point for output matching network design.
04
Design output matching network (OMN): Transform 50 Ω to R_opt at the device drain. This is the most critical network — maximises power transfer and efficiency. Design on Smith chart.
05
Design input matching network (IMN): Match 50 Ω to the device gate input impedance to maximise gain. Also affects noise figure and stability.
06
Bias circuit design: Set quiescent Ids for Class AB operation (10–15% Idss). Add stability resistors, bias feed inductors, bypass capacitors.
07
Stability analysis: Check K > 1 and |Δ| < 1 at ALL frequencies — especially well below and above the band where gain is highest. Add stabilisation resistors if needed.
08
Thermal design: Calculate junction temperature at full Pout. Size heatsink or copper pour. Derate Pout if T_j exceeds 150°C (GaAs) or 225°C (GaN).
09
EM simulation + PCB layout: EM-simulate all transmission line matching networks. Verify S-parameters match design. Add ground vias at every <λ/20 interval.
10
Measure and iterate: Measure Pout, PAE, S11, S21, ACPR on bench. Run load-pull to verify actual vs simulated optimum impedance. Retune if needed.
02 — Device Selection
Transistor Selection
The transistor is the hardest design decision to change later — once your PCB is laid out around a specific package, switching devices requires a respin. Read the datasheet load-pull data carefully before committing.
| Parameter | What to Check | Why |
|---|---|---|
| Pout vs freq | Is rated Pout achievable at your frequency? | GaN devices derate 1–2 dB per doubling of frequency |
| PAE at Pout | Load-pull PAE contours at your Pout | Datasheet headline PAE is often at max power, not your backoff point |
| Gain | Small-signal and large-signal gain at f | Low gain → more driver stages needed → more total power consumption |
| P1dB vs Pout | How much headroom above P1dB is Psat? | More headroom = less distortion at your Pout level |
| Thermal resistance | Rth_junction_to_case (°C/W) | Determines heatsink requirement at rated power |
| Impedance | Zin and Zopt at frequency | Very low impedance (e.g. 2+j1 Ω) needs high-Q matching — lossy, narrowband |
| Package | Flange, SMD, bare die, QFN | Flange easiest for thermal. SMD fine to 10 GHz. Bare die for MMIC |
Reference designs save months: Every major transistor vendor (Wolfspeed, MACOM, Qorvo, Infineon) publishes complete PA reference designs — PCB gerbers, BOM, S-parameter files, load-pull data. Start from a reference design for your frequency and power level. Use their EM-validated matching network as your starting point and only optimise from there.
03 — Load-Line Analysis
Load-Line Analysis & R_opt
The load line is drawn on the transistor I-V plane to determine the optimal load impedance. For maximum output power, the load line must use the full available voltage swing and current swing simultaneously — without hitting knee voltage or saturation current.
Optimal Load Resistance
R_opt = (V_DD − V_knee) / I_max (linear — single-ended Class AB)P_out_max = (V_DD − V_knee)² / (2·R_opt) = I_max·(V_DD − V_knee) / 2 (watts)
I_Q ≈ 10–15% × I_DSS (Class AB quiescent current)
V_DS_swing = V_DD − V_knee (one-sided) → 2×(V_DD − V_knee) peak-to-peak
V_knee ≈ 2–5 V (GaN), 0.5–1.5 V (GaAs), 3–5 V (LDMOS)
Worked Example — R_opt for 10W GaN PA at 3.5 GHz
Example 1 — Wolfspeed CGH40010 GaN HEMT, V_DD=28V, I_max=1.8A
1
V_knee ≈ 3 V (from I-V curves) · V_DD=28 V · V_swing=28−3=25 V
2
R_opt = V_swing / I_max = 25/1.8 = 13.9 Ω
3
P_out_max = 25²/(2×13.9) = 625/27.8 = 22.5 W — headroom above our 10 W target ✓
4
For 10 W operation: back off to R_load = 25²/(2×10) = 31.25 Ω — need to transform 50 Ω → 31.25 Ω at output
5
Alternatively, aim for Psat=22 W and operate at 10 W (3.4 dB back-off) → higher linearity
✓ R_opt = 13.9 Ω (full power) or ~31 Ω (10 W operating point). Output matching network must transform Z_load = 50 Ω → R_opt. Transformation ratio = 50/13.9 = 3.6:1.
R_opt vs S-param matching: Small-signal conjugate match gives Γ_MS from S22* — maximum power transfer in linear regime. Large-signal R_opt is found from load pull or I-V curves — maximum saturated power in nonlinear regime. For a PA, always use load-pull R_opt, not S22*. They can differ by 3–10× for high-power GaN devices.
04 — Output Matching Network
Output Matching Network Design
The output matching network (OMN) transforms the 50 Ω load to R_opt at the transistor drain. It must also present the correct harmonic impedances (short for Class F, open for Class F⁻¹) and must handle the full PA output current without saturating inductors or excessive resistive loss.
Lumped LC Matching (≤2 GHz)
L-Network Design (R_S < R_L)
For matching R_opt (source) to 50 Ω (load), with R_opt < 50 Ω:Q = √(R_L/R_S − 1) = √(50/R_opt − 1)
X_S = Q·R_S (series reactance, inductor if positive)
X_P = R_L/Q (shunt reactance, capacitor if positive X_S)
L = X_S/(2πf) · C = 1/(2πf·X_P)
Example 2 — L-network: 13.9 Ω → 50 Ω at 2.4 GHz
1
Q = √(50/13.9 − 1) = √(3.60−1) = √2.60 = 1.612
2
X_S = Q·R_S = 1.612×13.9 = 22.4 Ω (series inductor)
3
X_P = R_L/Q = 50/1.612 = 31.0 Ω (shunt capacitor)
4
L = 22.4/(2π×2.4×10⁹) = 1.49 nH (bond wire + trace!)
5
C = 1/(2π×2.4×10⁹×31.0) = 2.14 pF
6
Bandwidth: BW = f₀/Q = 2400/1.612 = 1.49 GHz (−3 dB bandwidth of matching network)
✓ L=1.49 nH, C=2.14 pF, BW=1.49 GHz. Note: 1.49 nH at 2.4 GHz is only a 1–2 mm bond wire or trace — parasitic inductance matters. Include transistor package parasitics in simulation.
Transmission Line Matching (≥2 GHz)
Above 2 GHz, lumped inductors become lossy and resonant — transmission line matching on the PCB is preferred. The quarter-wave transformer and single-stub tuner are the most common techniques.
Quarter-Wave Transformer
Z_TL = √(R_opt × 50) (characteristic impedance of λ/4 line)Length = λ_g/4 = c/(4f√ε_eff) at design frequency
BW ≈ 100%/Q (inherently narrowband — use multi-section for >20% BW)
For CGH40010 example: Z_TL = √(13.9 × 50) = √695 = 26.4 Ω
On Rogers RO4350B (εr=3.66): Z=26.4 Ω → W≈6 mm at 3.5 GHz → feasible
Harmonic termination matters for efficiency: A Class AB PA running near compression generates significant 2f₀ and 3f₀ drain current. Presenting a short circuit at 2f₀ (Class F) and open at 3f₀ boosts PAE by 10–15%. This is done with transmission line stubs or resonators in the OMN — standard in 5G NR base station PAs.
05 — Input Matching
Input Matching Network
The input matching network (IMN) transforms 50 Ω to the transistor gate impedance Z_in. Unlike the OMN, the IMN handles small signal levels so loss requirements are more relaxed — but it critically affects gain, stability, and noise.
| IMN Design Goal | Target Impedance | Trade-off |
|---|---|---|
| Maximum gain | Γ_MS = S11* (conjugate match) | May be unstable — check K factor first |
| Minimum NF | Γ_opt (noise optimal) | Gain sacrifice — Γ_opt ≠ Γ_MS in general |
| Stability | Inside stability circles on Smith chart | May sacrifice gain to ensure K>1 |
| Flat gain vs freq | Mismatch deliberately introduced at low f | Traded gain vs bandwidth flatness |
PA gate impedance is capacitive and low: A typical GaN HEMT gate looks like 2−j8 Ω at 3.5 GHz — Q factor of 4. Matching 50 Ω to this requires a high-Q network. Quality factor of the matching network must exceed device Q or insertion loss degrades gain. Use short transmission lines and avoid lossy chip inductors at these impedances.
06 — Bias Circuit Design
Bias Circuit Design
The bias network does three things: sets the quiescent operating point, provides a stable supply immune to RF feedback, and protects the transistor from thermal runaway. For GaN PAs, the gate bias is negative (typically −2 to −4 V) — requiring a negative supply or charge pump.
Drain Bias Feed
Drain Bias Network
RF choke (RFC): high impedance at f₀, low DC resistanceZ_RFC = 2πf₀·L ≫ R_opt → L ≫ R_opt/(2πf₀)
Example: R_opt=14 Ω at 3.5 GHz → L ≫ 14/(2π×3.5×10⁹) = 0.64 nH → use L ≥ 10 nH (15× margin)
Bypass caps: C_bypass resonates RFC at sub-harmonic frequencies → prevents oscillation
Use C in parallel: 100 pF (HF), 1 nF, 10 nF, 100 nF, 10 μF (bulk) — spans 6 decades of frequency
Active Bias for Thermal Stability
GaN and GaAs HEMTs have negative temperature coefficient of Ids — as temperature rises, Ids falls. This is self-protecting against thermal runaway (unlike BJTs). However, Vgs for a fixed Ids shifts with temperature — so a fixed gate voltage source causes Ids to drift with temperature. An active bias circuit compensates:
Example 3 — Active gate bias using a matched diode or BJT
Problem: GaN HEMT, Vgs(T) shifts −4 mV/°C. At ΔT=+50°C → ΔVgs=−200 mV → Ids changes significantly.
1
Solution 1 — Diode compensation: A diode in the gate bias voltage divider tracks temperature at −2 mV/°C (Si diode). Use 2 diodes for −4 mV/°C match. Mount diode thermally coupled to transistor.
2
Solution 2 — MMIC bias controller IC: Use a dedicated bias controller (e.g. Analog Devices ADL5610, Microchip MCP1402). Senses temperature, adjusts Vgs to maintain constant Ids across −40 to +85°C.
3
Verify: Measure Ids at 25°C and 85°C with active bias. Should be within ±5% of target.
✓ Active bias maintains constant Ids = 150 mA (10% Idss) across temperature. Without compensation: Ids drifts ±40 mA which shifts P1dB by ±1.5 dB — unacceptable for base station operation.
07 — Stability
PA Stability Analysis
PA stability is more challenging than LNA stability because: (1) the transistor is driven into its nonlinear region, (2) harmonic impedances matter, (3) the bias network creates potential feedback paths, and (4) the device gain is highest at low frequencies where the matching network provides no attenuation.
Stability Factors (from small-signal S-params)
K = (1 − |S11|² − |S22|² + |Δ|²) / (2|S12||S21|) (Rollett factor)|Δ| = |S11·S22 − S12·S21| (determinant)
Unconditionally stable: K > 1 AND |Δ| < 1 at ALL frequencies
μ = (1−|S11|²) / (|S22 − S11*·Δ| + |S12·S21|) (μ-factor — single condition, μ > 1 = stable)
PA stability must be checked from DC to 10× the operating frequency!
Stabilisation Techniques
| Technique | Where Added | Effect | Penalty |
|---|---|---|---|
| Series gate resistor | Between gate pad and matching network | Reduces K degradation at low f — adds loss to feedback path | Gain loss: each Ω = ~0.5–1 dB at GHz |
| RC feedback (shunt at gate) | RC to ground at gate node | Broadband stabilisation without excessive gain loss | Slight NF degradation |
| Source inductance | Bondwire or via inductance at source/emitter | Reduces gain at high frequency (negative feedback) | Reduces gain — can be modelled in simulation |
| Lossy input network | IMN with deliberate loss at unstable frequencies | Reduces gain below K=1 boundary | Lower gain in operating band too |
| Low-f absorber | RC in drain bias feed, shunted below band | Absorbs low-frequency oscillation energy without affecting RF | Minimal — bias feed absorber |
PAs are most likely to oscillate at low frequencies: At 100 MHz, a 10 GHz GaN device has 20–30 dB more gain than at 10 GHz. The matching networks present a high impedance at 100 MHz (not 50 Ω), potentially creating the gain + feedback loop needed for oscillation. Always run stability analysis from 10 MHz to 3× operating frequency. A good simulation tool is the Rollett factor K plotted vs frequency — check the whole curve, not just in-band.
08 — Thermal Management
Thermal Design
PA thermal design determines reliability and maximum output power. The transistor junction temperature T_j must stay below the maximum rated temperature — typically 150°C for GaAs, 225°C for GaN on SiC — under worst-case conditions (max Pout, max ambient, no airflow).
Thermal Resistance Chain
T_j = T_amb + P_diss × (θ_jc + θ_cs + θ_sa) (°C)P_diss = P_DC − P_out = P_out × (1/PAE − 1) (watts dissipated as heat)
θ_jc = junction-to-case (from datasheet) · θ_cs = case-to-heatsink (thermal paste) · θ_sa = heatsink-to-ambient
Thermal paste: θ_cs ≈ 0.1–0.5 °C/W · Natural convection heatsink: θ_sa ≈ 5–20 °C/W
Forced air: θ_sa ≈ 1–5 °C/W · Liquid cooling: θ_sa ≈ 0.1–0.5 °C/W
Worked Example — Junction Temperature
Example 4 — CGH40010 10W GaN, PAE=45%, T_amb=70°C
1
P_diss = P_out × (1/PAE − 1) = 10 × (1/0.45 − 1) = 10 × 1.222 = 12.2 W
2
θ_jc (CGH40010) = 4.4 °C/W (datasheet) · θ_cs = 0.3 °C/W (thermal paste) · θ_sa = 8 °C/W (natural conv.)
3
T_j = 70 + 12.2 × (4.4 + 0.3 + 8) = 70 + 12.2 × 12.7 = 70 + 154.9 = 224.9°C ← EXCEEDS max 225°C by 0.1°C — marginal!
4
Fix: upgrade heatsink to θ_sa = 5 °C/W → T_j = 70 + 12.2 × 9.7 = 70 + 118.3 = 188°C — 37°C margin ✓
5
Or: improve PAE to 55% → P_diss = 10×(1/0.55−1) = 8.18 W → T_j = 70+8.18×12.7 = 173.9°C ✓
✓ Natural convection insufficient for this PA at 70°C ambient. Use forced air heatsink (θ_sa=5°C/W) or improve PAE. Every 10°C of T_j reduction doubles MTTF (mean time to failure) — thermal design directly determines field reliability.
09 — PCB Layout
PA PCB Layout Rules
| Rule | Why | Consequence if Broken |
|---|---|---|
| Ground via fence every λ/20 | Prevents substrate modes and surface waves | Oscillation, gain ripple, unexpected radiation |
| Solid copper under transistor | Thermal path to heatsink or copper pour | Junction temperature 20–50°C higher |
| Minimum trace length at drain/gate | Every mm of trace = ~0.5–1 nH parasitic | Shifts matching network resonance — detuned |
| Separate input/output ground paths | Prevents output-to-input coupling | Oscillation via common ground impedance |
| Bypass caps as close as possible to DC pads | Minimises resonant inductance in bias feed | Bias feed becomes antenna — radiates harmonics |
| Use Rogers substrate (not FR4) above 2 GHz | FR4 tan δ = 0.02 vs Rogers 0.0037 — 5× lower loss | OMN/IMN loss reduces PAE by 3–8% |
| Shield input from output | Prevents RF leakage coupling | Reduced isolation → instability or reduced gain flatness |
| Keep bias lines short and decoupled | Long bias lines couple RF onto supply | Radiated emissions, supply modulation, oscillation |
Rogers RO4350B is the standard RF PA substrate: εr=3.66, tan δ=0.0037, copper-clad, available in 0.508 mm (20 mil) and 0.762 mm (30 mil). 20 mil for compact designs, 30 mil for easier manufacturing. RO4350B is processable on standard FR4 production lines — no exotic handling needed. Cost is 3–5× FR4 but essential above 2 GHz for PA work.
10 — Measurement
PA Measurement & Verification
| Measurement | Equipment | What to Check |
|---|---|---|
| S-parameters (small signal) | VNA (2-port) | S11 (input match), S21 (gain), S22 (output match), K stability factor |
| P1dB | Signal generator + power meter | Compress gain by 1 dB — verify matches datasheet at your frequency |
| PAE vs Pout | Sig gen + power meter + current probe | PAE = (Pout−Pin)/PDC — plot vs Pout sweep |
| ACPR | Signal generator (modulated) + spectrum analyser | Adjacent channel power ratio at specified offset — must meet standard mask |
| Harmonics | Spectrum analyser + harmonic filter | 2f₀, 3f₀ levels — must meet regulatory spurious emission limits |
| Thermal imaging | IR camera | Identify hot spots — gate pad should be coolest, drain hottest |
| Load pull | Load pull tuner system (Maury, Focus) | Map PAE and Pout vs Γ_load — verify simulation matches measurement |