Oscillator Theory — VCO & Crystal

Condition 1 — Magnitude: |A(jω₀) · β(jω₀)| = 1
The loop gain must be exactly unity at the oscillation frequency ω₀.
If |Aβ| > 1: oscillation grows (startup)   If |Aβ| < 1: oscillation decays   If |Aβ| = 1: sustained

Condition 2 — Phase: ∠A(jω₀) · β(jω₀) = 0° (or 360°)
The total phase shift around the loop must be 0°. This selects the oscillation frequency — only one frequency satisfies both conditions simultaneously.

Resonant frequency: f₀ = 1 / (2π√(LC))
Q factor: Q = ω₀L/R_s = 1/(ω₀CR_s) where R_s = series resistance of inductor
3 dB bandwidth: BW = f₀/Q
Peak impedance: Z_peak = Q²·R_s = L/(C·R_s)

Loaded Q vs Unloaded Q:
1/Q_L = 1/Q_u + 1/Q_ext   Always: Q_L < Q_u
Phase noise depends on Q_L — maximise it by minimising loading of the tank.

|R_neg| > R_tank   (typically target 2–3× for corners)
For cross-coupled CMOS pair: R_neg = −2/gm
Startup: gm > 1/R_tank = R_s·(ω₀C)² / ... or simply: gm·R_tank > 1 (loop gain > 1)

C_j(V) = C_j0 / (1 − V/φ)^m
C_j0 = zero-bias junction capacitance, φ = built-in potential (≈0.7 V silicon), m = grading coefficient
m = 0.5 abrupt junction, 0.33 linear graded, ≈1.0 hyperabrupt (engineered for linear f-vs-V)

Key issue: The C-V curve is nonlinear → K_vco (MHz/V) varies across tuning range → PLL loop bandwidth changes. Hyperabrupt varactors give more uniform K_vco — preferred in PLL VCOs.

K_vco = df/dV_tune   (MHz/V or GHz/V)
Typical: 10–500 MHz/V for RF VCOs at 0.5–10 GHz

Higher K_vco → wider tuning but more FM noise from supply voltage ripple:
PN_supply ≈ 20·log₁₀(K_vco × V_noise / Δf)
For K_vco = 100 MHz/V, V_noise = 100 nV/√Hz at Δf = 100 kHz: PN_supply = −80 dBc/Hz

This is why a low K_vco and a clean, well-decoupled VCO supply are critical design priorities.

1. Switched capacitor banks: Binary-weighted cap array for coarse tuning, small varactor for fine tuning. Varactor swing stays small → Q preserved.
2. Multiple VCO cores: Each covers a narrow sub-band (e.g. 4 VCOs × 15% TR = 60% total coverage).
3. Hyperabrupt varactors: Better tuning efficiency → smaller C_var needed → lower varactor loss.
4. Dual-loop PLL: Coarse integer-N loop + fine fractional-N loop working together.

L(Δf) = 10·log₁₀ { (2FkT/P_sig) · [1 + (f₀/2Q_L·Δf)²] · [1 + f_c/|Δf|] }

F = oscillator noise factor (excess noise)   k = 1.38×10⁻²³ J/K   T = 290 K
P_sig = output power (Watts)   f₀ = oscillation frequency   Q_L = loaded Q
Δf = offset from carrier   f_c = 1/f corner frequency of active device

Thermal floor (Δf → ∞): L_floor = 10·log₁₀(2FkT/P_sig)
At P = 0 dBm, F = 0 dB: floor = −171 dBc/Hz

Key levers: Double Q_L → −6 dB. Double P_sig → −3 dB. Halve F → −3 dB. Lower f_c (GaAs/SiGe vs CMOS) → narrows 1/f³ region.

Series branch: Lm (motional inductance) + Cm (motional capacitance) + Rm (motional resistance)
Shunt: C₀ (package + electrode capacitance, 1–5 pF)

Typical values: Lm = 1–100 mH, Cm = 0.001–0.1 pF, Rm = 1–100 Ω, C₀ = 1–5 pF

Series resonance: fs = 1/(2π√(Lm·Cm))
Parallel resonance: fp = fs · √(1 + Cm/C₀) — slightly above fs (<1% gap)
Q = ω_s·Lm/Rm — typically 10,000 to 500,000

Between fs and fp the crystal looks inductive — this is the operating region for Colpitts crystal oscillators. External load capacitance C_L trims the frequency:
f_L = fs · [1 + Cm/(2(C₀ + C_L))]

AT-cut (most common): 35°15' from X-axis. Cubic f-vs-T curve. Deviation ±5–30 ppm over −40°C to +85°C. Used in virtually all XO and TCXO.

SC-cut (Stress Compensated): Doubly-rotated. Flat f-vs-T curve near 75–85°C — used in OCXOs where oven is set in this flat region. Achieves ±0.01–0.1 ppm.

TCXO correction: Measures temperature, applies compensating V_ctrl to a varactor → ±0.5–2 ppm
OCXO correction: Heats crystal to SC-cut flat region → ±0.001–0.01 ppm (but 0.5–3 W heater)

① Maximise loaded Q: Q_L is dominant. Use thick metal inductors, avoid vias through the inductor loop, connect tank to high-impedance node. Target Q_L > 0.5×Q_u.

② Use switched-cap banks for coarse tuning: Keep varactor swing ≤30% of C_fixed. Large cap banks for coarse, small varactor for fine tuning. Preserves varactor Q.

③ Minimise K_vco: Just enough for temperature + process drift. Target 50–150 MHz/V for 2.4 GHz VCO. Each decade lower in K_vco = 20 dB lower supply FM noise.

④ Keep K_vco variation under 2× across tuning range: PLL loop bandwidth varies with K_vco → instability if it changes >4×. Use hyperabrupt varactor or digital K_vco compensation.

⑤ Optimise bias current: Phase noise improves with I_bias until current crowding / triode region. Sweet spot: transistors at peak gm/I_D. Simulate 3 dB vs 2 mA steps.

⑥ Clean VCO supply: Use a dedicated LDO. Decouple with 10 nF + 1 nF ceramics within 0.5 mm of the VCO supply pin. Aim <10 Ω supply impedance at all FM-relevant frequencies.

⑦ Substrate isolation: Use deep n-well, guard rings, >100 μm separation from digital clock nets. Substrate-injected switching noise is a primary phase noise degradation mechanism.

⑧ Startup margin at corners: Verify gm×R_tank > 3 at slow/cold corner. Use a short startup bias boost (2× I_ss for first 10 μs) if marginal.

⑨ Always buffer the VCO output: Direct connection to divider or mixer causes load pulling. Use a cascode or common-source buffer. Buffer noise contribution is negligible (sees large VCO signal).

⑩ Crystal load capacitance: PCB must present the specified C_L (typically 12 or 18 pF) to the crystal including stray capacitance. Incorrect C_L shifts frequency by several ppm — critical for GPS/cellular.