ADC Noise, Quantization & Thermal Noise Floor

01 — The Fundamental Limit

Quantization Noise

Every ADC maps a continuous analog voltage to a discrete digital code. The difference between the true analog value and the nearest quantization level is the quantization error. This error is unavoidable — it is the fundamental noise introduced by the digitization process itself, independent of temperature, bandwidth, or circuit quality.

SNR_ideal = 6.02·N + 1.76 dB

N = number of bits · Each additional bit adds exactly 6.02 dB of SNR
This is the theoretical maximum SNR set purely by quantization — assumes full-scale sine wave input

Where Does 6.02·N + 1.76 Come From?

Quantization noise derivation

An N-bit ADC has 2ᴺ levels, each of width Δ = V_FS / 2ᴺ (LSB size)
Quantization error uniformly distributed: −Δ/2 to +Δ/2
σ²_q = Δ²/12 = V²_FS / (12·2²ᴺ) (quantization noise power)
Full-scale sine wave power: P_sig = (V_FS/2)² / 2 = V²_FS/8
SNR = P_sig/σ²_q = (V²_FS/8) / (V²_FS/(12·2²ᴺ)) = (3/2)·2²ᴺ
SNR(dB) = 10·log₁₀((3/2)·2²ᴺ) = 10·log₁₀(1.5) + 20·N·log₁₀(2)
= 1.76 + 6.02·N dB

Worked Example — 12-bit ADC

Example 1 — AD9627 12-bit ADC at 160 MSPS, V_FS = 2 V pp

Ideal SNR = 6.02×12 + 1.76 = 74.0 dBFS

LSB size Δ = 2V / 2¹² = 2/4096 = 488 μV

Quantization noise RMS = Δ/√12 = 488/3.464 = 141 μV RMS

Noise spread across Nyquist BW = fs/2 = 80 MHz

Quantization noise PSD = σ²_q / (fs/2) = (141μ)²/80×10⁶ = 2.49×10⁻¹⁶ V²/Hz = −156 dBV²/Hz

Quantization noise floor = −156 dBV²/Hz → in dBFS/Hz: −156 − 20·log₁₀(1V_FS/2) = ~−154 dBFS/Hz

✓ 12-bit ADC ideal SNR = 74.0 dBFS. Quantization noise floor ≈ −154 dBFS/Hz at 160 MSPS. Each added bit: +6 dB SNR, noise floor drops 6 dB.

Bits (N)	Ideal SNR	LSB (2V FS)	Dynamic Range	Typical Application
8-bit	49.9 dB	7.8 mV	48 dB	Video, low-cost SDR
10-bit	61.9 dB	1.95 mV	60 dB	Oscilloscopes, general RF
12-bit	74.0 dB	488 μV	72 dB	IF digitisers, communications
14-bit	86.0 dB	122 μV	84 dB	Base station, radar receivers
16-bit	98.1 dB	30.5 μV	96 dB	Test equipment, audio, instruments
24-bit	146.2 dB	119 nV	144 dB	Delta-sigma audio, seismic — theory only; thermal noise dominates long before this

24-bit ADCs don't actually give 146 dB SNR: Thermal noise from the resistors and amplifiers in the signal chain will dominate long before the quantization noise. The theoretical limit of 146 dB is never reached in practice. This is exactly the relationship explored in the next section.

02 — The Physics Limit

Thermal Noise Floor

Thermal noise (Johnson-Nyquist noise) arises from the random motion of electrons in any resistive element at temperature T. Unlike quantization noise, it cannot be reduced by adding bits — it is set by the laws of thermodynamics. It sets an absolute minimum noise floor that no ADC or amplifier can overcome.

P_noise = k·T·B

k = 1.381×10⁻²³ J/K (Boltzmann) · T = temperature (Kelvin) · B = bandwidth (Hz)
At T=290 K (17°C): kTB = −174 dBm/Hz — the famous thermal noise floor

The −174 dBm/Hz Thermal Noise Floor

Thermal noise derivation

P_noise = kTB (watts) · k=1.381×10⁻²³, T=290K, B=1Hz
P_noise = 1.381×10⁻²³ × 290 × 1 = 4.0×10⁻²¹ W
= 4.0×10⁻¹⁸ mW → 10·log₁₀(4.0×10⁻¹⁸) = −174 dBm/Hz at 290 K

For bandwidth B (Hz): P_noise(dBm) = −174 + 10·log₁₀(B)
Examples: 1 MHz BW → −174+60 = −114 dBm · 80 MHz BW → −174+79 = −95 dBm

With amplifier noise figure NF: P_noise = −174 + NF + 10·log₁₀(B) dBm

Noise Figure and System Noise Floor

In a real receiver, thermal noise from the antenna, LNA, mixer and ADC driver all add together before the ADC input. The noise figure (NF) of the chain quantifies this degradation above the theoretical −174 dBm/Hz floor.

System noise floor with NF

NF_sys = NF_1 + (NF_2−1)/G_1 + (NF_3−1)/(G_1·G_2) + … (Friis formula, linear)
Noise floor = −174 dBm/Hz + NF_sys(dB) + 10·log₁₀(B_Hz)
MDS (min detectable signal) = Noise floor + SNR_required

Typical front-end NF: LNA 1–2 dB, Mixer 7–10 dB, ADC driver 10–15 dB
System NF dominated by first stage (LNA) — that is why LNA NF matters most

Example 2 — System noise floor for a 12-bit ADC receiver chain

Chain: LNA (NF=2 dB, G=20 dB) → Mixer (NF=8 dB, G=−6 dB) → ADC driver (NF=12 dB, G=15 dB) → 12-bit ADC at 160 MSPS

NF_sys (Friis, linear): F_1=1.585, F_2=6.31, F_3=15.85, G_1=100, G_2=0.25

F_sys = 1.585 + (6.31−1)/100 + (15.85−1)/(100×0.25) = 1.585+0.053+0.594 = 2.232 → NF=3.49 dB

Thermal noise floor at BW=80 MHz: −174+3.49+10·log₁₀(80×10⁶) = −174+3.49+79.0 = −91.5 dBm

Quantization noise floor (from Example 1): ≈ −154 dBFS/Hz × 80 MHz = −154+79 = −75 dBFS referred to ADC input

ADC input full scale = +4 dBm (typical) → quantization noise = −75+4 = −71 dBm referred to input before ADC

Thermal noise = −91.5 dBm vs Quantization noise = −71 dBm → thermal is 20 dB lower — not the limit!

✓ Thermal noise floor (−91.5 dBm) is well below quantization noise (−71 dBm). The 12-bit ADC quantization noise dominates. Adding more gain before the ADC raises both the signal AND the thermal noise identically — but does NOT help the quantization noise. This is the key insight.

03 — The Critical Relationship

Quantization Noise vs Thermal Noise

These two noise sources compete to determine your system's actual noise floor. Understanding which one dominates — and how to manage the crossover — is one of the most important skills in RF system design.

Property	Quantization Noise	Thermal Noise
Origin	Rounding to discrete levels	Random electron motion (physics)
Reducible by more bits?	Yes — +6 dB per bit	No — fundamental limit
Reducible by cooling?	No	Yes — scales with T (Kelvin)
Reducible by bandwidth?	Yes — filtering narrows Q-noise BW	Yes — P_noise = kTB
Reducible by oversampling?	Yes — OSR gain + noise shaping	Partial — averaging reduces effective BW
Reducible by gain before ADC?	Yes — raises signal above Q-floor	No — gain raises thermal noise equally
Affected by input signal level?	Yes — worst at low input levels	No — constant PSD regardless of signal
Frequency distribution	Flat (white) across 0 to fs/2	Flat (white) — Johnson noise

The Crossover Point — When Does Thermal Dominate?

The total noise floor is the power sum of thermal and quantization noise. Whichever is larger by more than ~10 dB dominates completely. There is a crossover point — a number of bits above which adding more bits gives no improvement because the thermal noise already dominates.

Crossover condition

Thermal noise referred to ADC input: P_th = −174 + NF_sys + 10·log₁₀(fs/2) dBm
Quantization noise at ADC input: P_q = P_FS − SNR_ideal = P_FS − (6.02N+1.76) dBm
Crossover when P_th = P_q:
N_crossover = (P_FS + 174 − NF_sys − 10·log₁₀(fs/2) − 1.76) / 6.02 bits

Below N_crossover: quantization noise dominates → more bits help
Above N_crossover: thermal noise dominates → more bits give no improvement

Example 3 — Finding the crossover bit depth (P_FS=+4 dBm, NF=3.5 dB, fs=160 MSPS)

P_th = −174 + 3.5 + 10·log₁₀(80×10⁶) = −174+3.5+79 = −91.5 dBm

N_crossover = (4 + 174 − 3.5 − 79 − 1.76) / 6.02 = 93.74 / 6.02 = 15.6 bits

So a 16-bit ADC with this front-end offers essentially the same noise floor as a 14-bit ADC!

To make use of 16 bits: need NF_sys < 3.5−(16−15.6)×6.02 = 3.5−2.4 = 1.1 dB — extremely difficult

✓ Crossover at ~15.6 bits. The front-end NF determines how many ADC bits are actually useful. For most practical RF receivers (NF 3–10 dB), 12–14 bits is the sweet spot. Beyond that, you are paying for bits that thermal noise is masking.

Noise Floor Visualiser

Quantization noise floor Thermal noise floor (kTB·NF) Effective noise floor (dominant) Dynamic range

Key design rule: Before specifying an ADC, first calculate N_crossover from your front-end NF and full-scale input. Spending money on bits above the crossover is wasted. Instead, invest in reducing the front-end NF (better LNA) — this lowers the thermal noise floor and raises the crossover bit depth, making more ADC bits useful.

04 — Sampling Regimes

Nyquist Zones & Aliasing

The ADC sampling frequency f_s divides the entire frequency axis into equal bands of width f_s/2 — called Nyquist zones. Zone 1 runs from 0 to f_s/2, Zone 2 from f_s/2 to f_s, Zone 3 from f_s to 3f_s/2, and so on. The crucial property: every zone aliases to exactly the same baseband image in Zone 1, but with alternating spectral polarity.

Nyquist zone definitions

Zone n spans: (n−1)·f_s/2 to n·f_s/2
f_alias = f_in mod f_s if result ≤ f_s/2, else f_s − result
Odd zones (1,3,5…): signal aliases with normal spectral polarity (no inversion)
Even zones (2,4,6…): signal aliases with inverted spectral polarity (spectrum flipped left-right)

Zone number: n = floor(f_in / (f_s/2)) + 1

Zone Map — Where Your Signal Goes

Zone	Frequency Range	Spectral Sense	Alias to Baseband	Common Use
Zone 1	0 – f_s/2	Normal	f_in (no alias)	Standard Nyquist sampling
Zone 2	f_s/2 – f_s	Inverted	f_s − f_in	Intentional IF undersampling
Zone 3	f_s – 3f_s/2	Normal	f_in − f_s	Direct RF sampling (L-band)
Zone 4	3f_s/2 – 2f_s	Inverted	2f_s − f_in	Bandpass sampling
Zone N (odd)	(N−1)f_s/2 – Nf_s/2	Normal	f_in − (N−1)f_s/2	High-IF direct sampling
Zone N (even)	(N−1)f_s/2 – Nf_s/2	Inverted ⇄	Nf_s/2 − f_in	High-IF direct sampling

Does the Nyquist Zone Affect SNR?

Quantization noise is spread uniformly across the entire Nyquist bandwidth (0 to f_s/2) regardless of which zone the input signal came from. So the SNR is the same in all zones — as long as the ADC's analog front-end (track-and-hold) maintains its noise performance up to the input frequency.

ADC bandwidth is the real limit for high-zone sampling: An ADC rated for f_s = 200 MSPS may only have a track-and-hold (T/H) analog bandwidth of 500 MHz or 1 GHz. Sampling a signal in Zone 8 (700–800 MHz with 200 MSPS ADC) requires the T/H to faithfully capture the 750 MHz signal. As input frequency rises, T/H distortion, aperture jitter, and NF all degrade. Check the "Full Power Input Bandwidth" spec on the ADC datasheet — signals above this frequency see significant SNR degradation even if f_in is theoretically resolvable.

Spectral Inversion in Even Zones — What to Do

When a signal aliases from an even Nyquist zone, the spectrum is flipped — what was the upper sideband appears as the lower sideband and vice versa. For a USB (upper sideband) signal in Zone 2, the aliased baseband output appears as LSB. This is easily corrected in digital:

Spectral inversion correction

Detected in even zone → conjugate the complex baseband samples: x[n] → x*[n]
Or equivalently: negate the Q channel of the IQ output → swaps USB↔LSB
Or: in real-only ADC output, reverse the frequency axis: f → (f_s/2 − f)
No hardware needed — pure DSP correction, zero cost

ADC Sampling Calculator — try all zones interactively →

4b — Clock Jitter Budget

ADC Clock Jitter Budget

Aperture jitter is the timing uncertainty of the ADC’s sampling instant. It converts directly to amplitude error at the input — a jitter of t_j seconds on a sinusoid of frequency f_in and amplitude A creates a voltage error of A·2πf·t_j. This noise grows with input frequency, creating a hard upper limit on achievable SNR regardless of bit depth.

Jitter-limited SNR and required clock jitter

SNR_jitter = −20·log₁₀(2π·f_in·t_j) dB (t_j = total RMS jitter in seconds)
t_j_required = 1 / (2π·f_in·10^(SNR_target/20)) seconds
Total jitter: t_j_total = √(t_j_clock² + t_j_aperture² + t_j_PLL²) (RMS sum)
Phase noise to jitter: t_j = √(2·∫ L(f)·df) / (2π·f_clk) (integrate phase noise PSD from f_low to f_high)

Required Clock Jitter Table

The table below shows the maximum allowable RMS clock jitter to achieve a given SNR target at each input frequency. If your jitter exceeds the value in the cell, the ADC SNR will be limited by jitter — not quantization noise.

Input Freq (f_in)	SNR = 60 dBFS (10-bit equivalent)	SNR = 74 dBFS (12-bit equivalent)	SNR = 86 dBFS (14-bit equivalent)	SNR = 98 dBFS (16-bit equivalent)
1 MHz	159 ps RMS	25.2 ps RMS	4.0 ps RMS	632 fs RMS
10 MHz	15.9 ps RMS	2.52 ps RMS	400 fs RMS	63 fs RMS
70 MHz (IF)	2.27 ps RMS	360 fs RMS	57 fs RMS	9 fs RMS
100 MHz	1.59 ps RMS	252 fs RMS	40 fs RMS	6 fs RMS
200 MHz	796 fs RMS	126 fs RMS	20 fs RMS	3 fs RMS
500 MHz	318 fs RMS	50 fs RMS	8 fs RMS	<2 fs RMS
1 GHz	159 fs RMS	25 fs RMS	4 fs RMS	<1 fs RMS

Green = achievable with standard crystal oscillator · Yellow = requires low-jitter clock buffer/PLL IC · Red = requires ultra-low-jitter source (e.g. LMX2820, Si5395, or ovenized OCXO)

Clock Source Selection Guide

Clock Source	Typical Jitter	Cost	Best For
Standard crystal oscillator (TCXO)	1–10 ps RMS	$1–5	Low-frequency ADC sampling, f_in < 10 MHz
Clock buffer IC (e.g. LMK00304)	100–500 fs RMS	$5–15	IF sampling up to 70 MHz, multi-ADC distribution
Jitter cleaner PLL (e.g. Si5395)	50–150 fs RMS	$15–40	IF digitisers, 5G/LTE base station clocking
Ultra-low jitter PLL (e.g. LMX2820)	15–50 fs RMS	$30–60	Direct RF sampling, high-zone undersampling, radar
OCXO + PLL (ovenized)	10–30 fs RMS	$100+	Test equipment, precision instruments
Cryogenic oscillator	<1 fs RMS	$10,000+	Quantum computing ADC, ultra-low-noise research

Example — Clock jitter budget for 14-bit ADC sampling at 70 MHz IF, f_s=200 MSPS

Target SNR = 86 dBFS (14-bit ideal) at f_in = 70 MHz

Required t_j = 1/(2π×70×10⁶×10^(86/20)) = 1/(2π×70×10⁶×63095) = 36 fs RMS

ADC internal aperture jitter (e.g. AD9694): t_j_ap = 60 fs RMS (datasheet)

Clock source budget: t_j_clock = √(36² − 60²) → impossible! ADC aperture alone exceeds target

Realistic target: SNR = −20·log₁₀(2π×70×10⁶×60×10⁻¹⁵) = 77.6 dBFS (12.9 effective bits)

To recover 86 dBFS at 70 MHz: need ADC with t_j_ap < 20 fs → choose ADS54J60 (15 fs aperture) + LMX2820 clock

✓ Jitter budget: ADC aperture dominates. Even a perfect clock doesn’t help if the ADC’s own aperture jitter is too high. Check the ADC datasheet “aperture jitter” spec first, then budget the clock jitter as the remainder using RMS sum: t_j_total = √(t_j_ap² + t_j_clock²).

Phase noise to jitter conversion: Clock oscillator datasheets give phase noise L(f) in dBc/Hz vs offset. Convert to jitter by integrating: t_j = (1/(2πf_clk))×√(2×∫L(f)df). Typical integration band is 12 kHz to 20 MHz. The LMX2820 achieves −99 dBc/Hz at 100 Hz offset and −165 dBc/Hz noise floor — integrating to <15 fs RMS. For comparison, a cheap 200 MHz crystal gives −90 dBc/Hz at 1 kHz, integrating to 1–2 ps RMS.

05 — More Samples, Less Noise

Oversampling & Noise Shaping

Oversampling — using f_s significantly larger than 2·f_in — spreads quantization noise across a wider bandwidth. When a digital filter then restricts the output to the signal bandwidth B, the out-of-band noise is removed. The result is an effective increase in SNR and ENOB.

Oversampling SNR gain

Oversampling ratio: OSR = f_s / (2·B) (signal bandwidth B, not f_s/2)
Simple oversampling gain: ΔSNR = 10·log₁₀(OSR) = 3 dB per octave of OSR
ENOB gain: ΔENOB = 0.5·log₂(OSR) = 0.5 bits per octave of OSR

With noise shaping (ΔΣ ADC, L-th order):
ΔSNR = 10·log₁₀(OSR^(2L+1)) = (2L+1)·10·log₁₀(OSR)
1st-order ΔΣ: 9 dB per octave · 2nd-order: 15 dB per octave · 5th-order: 33 dB per octave

OSR SNR Gain — Worked Example

Example 4 — 16-bit audio ADC with OSR=256, 2nd-order noise shaping

Base SNR (16-bit): 6.02×16+1.76 = 98.1 dBFS

Simple oversampling gain: 10·log₁₀(256) = +24 dB → effective SNR = 122 dBFS

With 2nd-order noise shaping (L=2): gain = 5·10·log₁₀(256) = 5×24 = +120 dB gain in theory

Practical limit: thermal noise, op-amp noise → real audio ΔΣ achieves 110–120 dBFS SNR

Effective ENOB: (120−1.76)/6.02 ≈ 19.6 bits — from a simple 1-bit comparator with noise shaping!

✓ Delta-Sigma ADCs use extreme oversampling (OSR 64–512) with high-order noise shaping to push quantization noise out of the signal band, achieving 20+ effective bits from a 1-bit core. This is how high-end audio DACs achieve 120+ dB dynamic range.

Noise budget at OSR=1 (no oversampling)100%

Quantization

Thermal

Other

Noise budget at OSR=64 (simple oversampling, filter to B)100%

Thermal (now dominates)

Other

Noise budget at OSR=64 with 2nd-order ΔΣ noise shaping100%

Thermal (completely dominates)

Other

As OSR and noise shaping order increase, quantization noise shrinks dramatically — until thermal noise completely takes over.

06 — Intentional Aliasing

Intentional Undersampling

Undersampling (bandpass sampling or IF sampling) deliberately samples a signal at f_s < 2·f_in, causing it to alias to a lower frequency. This is not an error — it is a powerful design technique that lets an ADC act as both a sampler and a downconverter, eliminating the need for an analog mixer stage.

Bandpass Sampling Rules

Bandpass sampling condition

Signal occupies band: f_L to f_H (bandwidth B = f_H − f_L)
Nyquist zone condition: the entire signal must fit within a single zone — no zone boundary splitting
f_s ≥ 2B (minimum sample rate — only need to sample the bandwidth, not the centre frequency!)
Valid sample rates: 2f_H/n ≥ f_s ≥ 2f_L/(n−1) for integer n=1,2,3,…
Choose n such that f_s is achievable and no zone boundary falls inside the signal band

Quantization noise: still spread across 0 to f_s/2 — so narrower B → better in-band SNR

IF Digitiser — Worked Example

Example 5 — 70 MHz IF, BW=10 MHz, target f_s=65 MSPS (Zone 3)

Signal: 65–75 MHz (10 MHz BW centred at 70 MHz)

f_s = 65 MSPS → f_s/2 = 32.5 MHz → Zone of 70 MHz: floor(70/32.5)+1 = floor(2.15)+1 = Zone 3

Zone 3 is odd → normal spectral polarity ✓ (no inversion needed)

Alias: f_alias = 70 − 65 = 5 MHz (centre of aliased signal)

Aliased band: 0–5 MHz → 0–5 MHz in baseband — check no zone boundary at 32.5 MHz splits signal (65–75 MHz is all in Zone 3) ✓

Q-noise floor: SNR = 6.02×12+1.76 = 74 dBFS over 32.5 MHz BW → in 10 MHz BW: SNR+10·log₁₀(32.5/10) = 74+5.1 = 79.1 dBFS

✓ 70 MHz IF signal aliases to 0–5 MHz baseband. No mixer needed. The 65 MSPS ADC acts as a free downconverter. SNR improves by 5.1 dB vs using the full Nyquist band, because only 10 MHz of the 32.5 MHz noise band contains the signal.

07 — Practical Performance

Dynamic Range, SFDR & ENOB

Real ADCs fall short of the ideal 6.02·N + 1.76 dB SNR due to thermal noise, nonlinearity, aperture jitter, and reference noise. The key practical specifications are SNDR (signal-to-noise-and-distortion ratio), SFDR (spurious-free dynamic range) and ENOB (effective number of bits).

Practical ADC performance metrics

SNDR = 10·log₁₀(P_signal / (P_noise + P_distortion)) dBFS (measured)
ENOB = (SNDR − 1.76) / 6.02 (effective bits from actual performance)
SFDR = distance from signal to worst spurious product (dBFS or dBc)
THD = total harmonic distortion — sum of all harmonic power

Aperture jitter contribution: SNR_jitter = −20·log₁₀(2π·f_in·t_j) dB
Total SNR: 1/SNR_total = 1/SNR_q + 1/SNR_thermal + 1/SNR_jitter (power sum)

ENOB vs Frequency — The Jitter Wall

At low input frequencies, ENOB ≈ N−0.5 (close to ideal, limited by thermal noise). As input frequency rises, aperture jitter becomes the dominant limit — causing ENOB to fall even though the digital word length stays N bits. This is the "jitter wall."

Example 6 — ENOB vs frequency for 14-bit ADC with t_j=100 fs RMS aperture jitter

SNR_jitter at 10 MHz: −20·log₁₀(2π×10⁷×100×10⁻¹⁵) = −20·log₁₀(6.28×10⁻⁶) = 104 dB

SNR_jitter at 100 MHz: −20·log₁₀(2π×10⁸×100×10⁻¹⁵) = 84 dB (−20 dB vs 10 MHz)

SNR_jitter at 1 GHz: 64 dB → ENOB = (64−1.76)/6.02 = 10.4 bits — from a 14-bit ADC!

Ideal 14-bit SNR = 86 dBFS → ENOB = 13.7 bits. At 1 GHz input: only 10.4 bits effective.

✓ Jitter is the limiting factor for high-zone direct sampling. 100 fs aperture jitter limits to 84 dBFS SNR at 100 MHz, 64 dBFS at 1 GHz. This is why high-speed ADCs for 5G and radar use ultra-low jitter clocks (often from a dedicated clock IC like LMX2820) with <50 fs RMS.

08 — Architecture Guide

ADC Architecture Comparison

Architecture	Speed	Resolution	Noise Type	Best For
Flash	Fastest (>1 GSPS)	6–8 bits	Thermal dominant	Oscilloscopes, radar wideband
Pipeline	Fast (50–3000 MSPS)	8–16 bits	Thermal + jitter	Communications, SDR, IF sampling
SAR	Medium (1–100 MSPS)	12–18 bits	Thermal + Q balanced	Instrumentation, data acquisition
Delta-Sigma	Slow (kHz–MHz audio)	16–32 bits	Quantization (noise shaped)	Audio, precision measurement, seismic
Interleaved	Very fast (up to 10+ GSPS)	8–12 bits	Mismatch spurs dominant	5G mmWave, optical, wideband radar

The right ADC depends on which noise you want to trade: Pipeline ADCs are the workhorse of RF — they balance speed and resolution, with thermal noise and jitter as the practical limits. Delta-sigma ADCs trade speed for extraordinary resolution by pushing quantization noise out of band. Flash ADCs maximise speed at the expense of resolution. In RF system design, you almost never need more than 14–16 bits before thermal noise dominates anyway.

09 — Try the Tools

Interactive Tools

Use the calculators below to explore every concept on this page — enter real ADC parameters and see where your signal aliases, what SNR you get, and how much margin you have above the noise floor.

ADC Sampling Calculator — Nyquist zones, alias freq, OSR, spectral inversion → RX Chain NF Calculator — system noise floor from LNA to ADC → RF Link Budget — MDS, SNR, received power → ADC & DAC Theory — SFDR, aperture jitter, ADC types → Noise in RF Systems — thermal, shot, flicker, phase noise →

Quantization Noise

Where Does 6.02·N + 1.76 Come From?

Worked Example — 12-bit ADC

Thermal Noise Floor

The −174 dBm/Hz Thermal Noise Floor

Noise Figure and System Noise Floor

Quantization Noise vs Thermal Noise

The Crossover Point — When Does Thermal Dominate?

Noise Floor Visualiser

Nyquist Zones & Aliasing

Zone Map — Where Your Signal Goes

Does the Nyquist Zone Affect SNR?

Spectral Inversion in Even Zones — What to Do

ADC Clock Jitter Budget

Required Clock Jitter Table

Clock Source Selection Guide

Oversampling & Noise Shaping

OSR SNR Gain — Worked Example

Intentional Undersampling

Bandpass Sampling Rules

IF Digitiser — Worked Example

Dynamic Range, SFDR & ENOB

ENOB vs Frequency — The Jitter Wall

ADC Architecture Comparison

Interactive Tools

ADC Noise and Dynamic Range in RF Systems

SNR, ENOB and SFDR

Clock Jitter Limitation