ADC & DAC for RF Systems

Required: f_s ≥ 2 · f_max
f_s = sampling rate (samples/second, Hz), f_max = highest frequency in signal
Nyquist frequency = f_s/2 = maximum unambiguous signal frequency
Nyquist zone 1 (baseband): 0 to f_s/2

In practice, use f_s ≥ 2.5×f_max to leave room for the anti-aliasing filter transition band.
A perfect brick-wall filter at f_s/2 is physically impossible — real filters need a transition band.

f_alias = |f_in − round(f_in/f_s) · f_s|
Or equivalently: f_alias = f_in mod f_s, then fold if > f_s/2

Example: f_s = 100 MHz, f_in = 130 MHz
f_alias = |130 − 100| = 30 MHz — the 130 MHz signal appears at 30 MHz

Example: f_s = 100 MHz, f_in = 270 MHz
270 mod 100 = 70 MHz — appears at 70 MHz (3rd Nyquist zone alias)

Rule: Every frequency outside 0–f_s/2 that reaches the ADC creates an alias inside 0–f_s/2.

Condition for alias to land in zone 1:
Choose f_s such that: 2·f_c/(n+1) ≤ f_s ≤ 2·f_c/n   where n = floor(f_c/BW)
f_c = centre frequency of bandpass signal, BW = bandwidth

Resulting alias frequency in zone 1:
f_alias = f_c − m·f_s where m = round(f_c/f_s)

Example: 70 MHz IF signal, 10 MHz bandwidth, sample at f_s = 56 MHz
m = round(70/56) = 1 → f_alias = 70 − 56 = 14 MHz
The 70 MHz IF appears at 14 MHz — a digital downconversion with no analogue mixer!

Example: 240 MHz IF, sample at f_s = 80 MHz
m = round(240/80) = 3 → f_alias = 240 − 3×80 = 0 MHz (at baseband!)

Key constraint: ADC must have input bandwidth ≥ f_IF, even if f_s ≪ f_IF. Most ADCs specify separate "full-power input bandwidth" for this reason.

Quantisation step size: Δ = V_FS / 2^N
Quantisation noise power: P_q = Δ²/12 = V_FS² / (12 · 2^(2N))

Ideal SNR for full-scale sine wave:
SNR_ideal = 6.02·N + 1.76   dB

N = number of bits
Every additional bit adds exactly 6.02 dB of SNR (doubles amplitude resolution)

Examples:
8-bit ADC: SNR_ideal = 49.9 dB
12-bit ADC: SNR_ideal = 74.0 dB
16-bit ADC: SNR_ideal = 98.1 dB
24-bit ADC: SNR_ideal = 146.2 dB (audio, near theoretical limit of CMOS)

Noise spectral density (NSD) of quantisation noise:
NSD = −SNR_ideal − 10·log₁₀(f_s/2)   dBFS/Hz
At f_s = 100 MHz, 12-bit: NSD = −74.0 − 10·log₁₀(50×10⁶) = −74.0 − 77.0 = −151 dBFS/Hz

SINAD (Signal-to-Noise-And-Distortion):
SINAD = signal power / (noise + all harmonic distortion power)
Measured with a full-scale sine wave input. Gives the total degradation including both noise and distortion.

ENOB (Effective Number Of Bits): ENOB = (SINAD − 1.76) / 6.02

ENOB tells you how many ideal bits the ADC actually delivers, accounting for all imperfections.
An 12-bit ADC with SINAD = 68 dB: ENOB = (68 − 1.76)/6.02 = 11.0 bits (1 bit lost to noise/distortion)

Noise floor (actual): NF = −SINAD − 10·log₁₀(f_s/2) dBFS/Hz

Typical ENOB loss from ideal:
 0.5–1.0 bit lost at low input frequencies (thermal + reference noise)
 1.0–2.0 bits lost at high frequencies (aperture jitter + input RC rolloff)
 2.0+ bits lost above the ADC’s rated bandwidth

Rectangular dither (RPDF): Uniform noise ±Δ/2. Eliminates coherent patterns. Adds noise power Δ²/12.
Triangular dither (TPDF): Sum of two RPDF sources. Better spectral whitening. Adds noise power Δ²/6.
Gaussian dither: Best psychoacoustic properties (audio). Adds σ² noise.

Dither amplitude: 0.5–1 LSB RMS is typical. Too much dither wastes dynamic range.
In high-speed RF ADCs, thermal noise often serves as natural dither — explicit dither rarely needed.
In precision audio ADCs (24-bit), dither is essential and carefully shaped (noise-shaping + dither).

SFDR = signal power − peak spurious tone power   (dBc or dBFS)

Typical values for RF ADCs:
Entry-level (8-bit at 1 GSPS): SFDR ≈ 50–60 dBc
Mid-range (12-bit at 500 MSPS): SFDR ≈ 70–80 dBc
High-performance (16-bit at 250 MSPS): SFDR ≈ 90–100 dBc

SFDR vs input level: SFDR typically degrades at full scale (saturation harmonics) and at very low levels (sub-LSB nonlinearity). Best SFDR is usually at −1 to −6 dBFS input.

SFDR sets the spurious-free receiving window:
If ADC SFDR = 70 dBc and desired signal is −60 dBFS, spurious tones reach −60 − 70 = −130 dBFS.
A blocker at 0 dBFS generates a spur at −70 dBFS — which may land on your desired signal at −60 dBFS.

THD = 10·log₁₀((P_H2 + P_H3 + P_H4 + ...) / P_fundamental)   dBc

P_H2, P_H3... = power of 2nd, 3rd... harmonics
Typical: 2nd harmonic 6–8 dB higher than 3rd in CMOS ADCs
Odd harmonics (3rd, 5th) fall within the signal band for bandpass signals — cannot be filtered

HD2 and HD3 alias back: f_H2 = 2·f_in mod f_s, f_H3 = 3·f_in mod f_s
These must be checked for each input frequency — aliased harmonics can fall on top of other signals.

Third-order intermodulation products: f_IM3 = 2f1−f2 and 2f2−f1

IIP3 of ADC: IIP3 = P_in + (SFDR_IM3)/2   (dBFS)
where SFDR_IM3 = signal-to-IM3 ratio at the specific input power P_in

Two-tone SFDR (IM3 limited):
At full scale, IM3 typically 6–10 dB worse than single-tone SFDR
Rule: back off input by 6 dB from full scale → IM3 drops by 12 dB (3rd order slope)

Intermodulation-free dynamic range (IMFDR3):
IMFDR3 = (2/3)·(SFDR_IM3 + NSD_bandwidth) — the range where IM3 is below the noise floor

SNR_jitter = −20·log₁₀(2π·f_in·σ_t)   dB

σ_t = RMS aperture jitter (seconds), f_in = input signal frequency

Examples at f_in = 100 MHz:
σ_t = 1 ps: SNR_jitter = −20·log(2π×10⁸×10⁻¹²) = 90 dB
σ_t = 0.1 ps: SNR_jitter = 110 dB
σ_t = 10 ps: SNR_jitter = 70 dB (limits to 11-bit performance!)

At f_in = 1 GHz (direct RF sampling):
σ_t = 0.1 ps: SNR_jitter = 90 dB (limited to ≈14.6 bits ENOB)
σ_t = 0.05 ps (50 fs): SNR_jitter = 96 dB (state of the art)

Total SNR with both jitter and quantisation noise:
SNR_total = −10·log₁₀(10^(−SNR_ideal/10) + 10^(−SNR_jitter/10))
The worse of the two dominates — jitter wins at high frequency, quantisation wins at low frequency.

σ_t = (1/(2π·f_clk)) · √(2·∫[f1,f2] L(f) df)   seconds RMS

L(f) = single-sideband phase noise of clock (dBc/Hz)
Integration limits: f1 = 10 Hz (or 1 kHz for most ADC specs), f2 = f_clk/2

Practical rule of thumb (integrating a typical oscillator spectrum):
OCXO at 100 MHz: σ_t ≈ 0.05–0.1 ps RMS
TCXO at 100 MHz: σ_t ≈ 0.3–1 ps RMS
XO at 100 MHz: σ_t ≈ 1–5 ps RMS
PLL-generated clock: σ_t ≈ 0.2–2 ps (depends heavily on PLL bandwidth and VCO quality)

For ADCs sampling above 100 MHz input frequencies, OCXO or ultra-low-jitter clock cleaner ICs (AD9516, LMK04832) are required to avoid jitter-limited SNR.

Zero-order hold frequency response: H(f) = sinc(πf/f_s) = sin(πf/f_s) / (πf/f_s)
At f = f_s/2: H = sinc(π/2) = 2/π ≈ 0.637 → −3.9 dB rolloff
At f = f_s/4: H = sinc(π/4) ≈ −0.91 dB

Images (spectral replicas): appear at f_out ± n·f_s for all integer n
A baseband signal from 0 to f_s/2 has images at f_s ± f_out, 2f_s ± f_out, etc.
These must be filtered by a reconstruction LPF or BPF before upconversion.

sinc pre-correction (sinc equalisation): Apply 1/sinc(πf/f_s) digitally before the DAC to flatten the passband response. Effective but boosts noise near f_s/2.

Mix-mode DAC: High-speed RF DACs (AD9162, DAC38RF82) can directly synthesise RF signals at 2nd or 3rd Nyquist zone — outputting signals at f_s to 3f_s/2. Replaces an analogue upconverter in some architectures.

Update rate: Modern RF DACs: 1–12 GSPS (AD9164: 6 GSPS, AD9172: 12 GSPS)
NSD (Noise Spectral Density): −155 to −165 dBFS/Hz for high-performance RF DACs
SFDR: 75–85 dBc at Nyquist (degrades with frequency, improves with backoff)
IM3: Typically 70–80 dBc at two tones at −6 dBFS

Segment switching DAC (thermometer coded): Used for the MSBs in high-performance DACs. Monotonic code transitions, low glitch, good linearity near full scale. Area-intensive.
Current-steering DAC: Standard for RF. Each bit switches a current source into one of two output paths. Speed limited by output node parasitic capacitance.
R-2R ladder DAC: Simple, low power, poor high-frequency performance. Used only for precision low-frequency applications.

Required stopband attenuation: A_stop ≥ SFDR (dBc) + blocker level above noise floor
For a receiver with 70 dBc SFDR and −10 dBFS blocker at fs/2:
A_stop ≥ 70 dB at f_s/2

Minimum filter order (Butterworth, −3 dB at f_c = f_pass):
n = log(10^(A_stop/10) − 1) / (2·log(f_stop/f_pass))

Practical rule for Nyquist sampling:
Use f_s ≥ 2.5×BW and a 5th–7th order elliptic or Chebyshev filter
An elliptic filter achieves the sharpest transition band for a given order — preferred for AAF

For undersampling (bandpass AAF):
BPF centred on IF, passband = signal BW, stopband at adjacent Nyquist zone boundaries
Must reject image band (f_IF ± n·f_s) by ≥ SFDR dBc

① Check jitter first, bits second: At f_in = 100 MHz, even a 16-bit ADC is limited by 1 ps jitter to 90 dB SNR (≈14.7 bits ENOB). Calculate SNR_jitter = −20·log(2π·f_in·σ_t) before choosing bit depth.

② Match ADC input bandwidth to sampling zone: For undersampling, the ADC must specify "full-power input bandwidth" ≥ f_IF. This is separate from f_s. A 200 MSPS ADC can have 1 GHz input bandwidth — check the datasheet.

③ Never allow any signal above (N_zone)·f_s/2 to reach the ADC: Design the AAF to attenuate all Nyquist zone boundaries by ≥ SFDR + 10 dB. A missed blocker at 2·f_s/2 aliases into the first zone and cannot be removed.

④ Input drive level: Most ADCs achieve best SFDR at −1 to −6 dBFS input. Driving full scale clips on any excess and degrades SFDR by 10–20 dB. Add a VGA stage or fixed attenuator to set operating point.

⑤ Clock source quality is paramount: Use the lowest-jitter available clock: OCXO (<0.1 ps) for high-IF sampling, VCXO + clock cleaner for PLL-derived clocks. Never use a CMOS logic clock for ADC sampling above 50 MSPS.

⑥ Differential clock input: Always use the ADC's differential clock input, not single-ended. Differential rejects common-mode supply noise that would otherwise modulate the clock edges. Drive with a differential LVDS or LVPECL clock buffer, not a CMOS gate.

⑦ Separate ADC analogue and digital supplies: The ADC's internal digital switching (code transitions, output drivers) injects noise onto the supply. Use separate LDOs for analogue and digital supply pins. Never share with digital logic supplies.

⑧ Reference voltage decoupling: The voltage reference sets the full-scale range. Any noise or ripple on V_ref appears as gain error modulation — directly as spurious tones. Decouple with 10 μF + 100 nF ceramics within 2 mm of the V_ref pin.

⑨ Differential input termination: RF ADCs typically want 100 Ω differential termination at the input. This is usually achieved with a balun + resistive termination or a fully differential op-amp driver. Match the ADC input network carefully — VSWR ripple on the input causes passband gain ripple.

⑩ Digital output interface: JESD204B/C is standard for high-speed ADCs above 500 MSPS. Each JESD lane carries ~12.5 Gbps serial data. Route JESD lanes as differential pairs, impedance-controlled to 100 Ω, ≤10 cm board length to minimise jitter accumulation.

⑪ For undersampling, verify alias placement at design time: Calculate f_alias = |f_IF − m·f_s| for each harmonic of f_IF (2·f_IF, 3·f_IF...). Any harmonic that aliases onto your wanted band creates permanent in-band distortion that cannot be removed by filtering.

⑫ FPGA/DSP interface latency: Pipeline ADCs have 8–16 clock cycle latency. This must be accounted for in closed-loop systems (DPD feedback, carrier aggregation timing). Time-interleaved ADCs also require per-core offset/gain/timing calibration in the FPGA.