RF Passives › Bias Networks

Bias Tee Designer

Design bias tees for LNA, PA, and mixer DC biasing. Computes RF choke inductance, DC-blocking capacitor value, insertion loss, lower/upper corner frequencies and frequency response plot. Includes component recommendations and practical layout rules.

// RF Operating Frequencies
MHz
MHz
Ω
Rule of thumb: f_low defines the choke and cap sizes. The bias tee must present high impedance (choke) and low impedance (cap) at f_low — f_high is used to check parasitic self-resonance margins.
// DC Supply Parameters
V
mA
Ω
dB
// Component Constraints
dB
dB
—
// Bias Tee Topology
RF IN C_block RF OUT L_choke DC Z₀ Z₀ blocks DC | passes RF blocks RF | passes DC
// Computed Component Values
RF Choke (Inductor)
Minimum L_choke required—
Recommended L_choke value—
Choke impedance at f_low—
Choke isolation at f_low—
Choke DC resistance (est.)—
Recommended choke series—
DC-Blocking Capacitor
Minimum C_block required—
Recommended C_block value—
Cap impedance at f_low—
Cap insertion loss at f_low—
Voltage rating required—
Bias Tee System Performance
Lower −3 dB corner f_L—
Upper choke SRF margin—
Estimated insertion loss—
DC voltage drop—
// Insertion Loss vs Frequency
Bias Tee IL (dB) −3 dB limit
// Design Equations
Choke minimum inductance: L_min = Z₀ × 10^(iso_dB/20) / (2πf_low)
→ For 40 dB isolation: L_min = Z₀ × 100 / (2πf_low)

Blocking cap minimum capacitance: C_min = 1 / (2πf_low × Z₀ × (10^(IL_dB/20) − 1))
→ For 0.1 dB insertion loss: C_min ≈ 1.6 / (2πf_low × Z₀)

Lower −3 dB frequency: f_L = 1 / (2π × C_block × Z₀)
Choke isolation: iso = 20·log(2πf·L / Z₀) dB
Cap insertion loss: IL = 20·log(√(1 + 1/(2πf·C·Z₀)²)) dB
Practical component selection guide:
• Choke: Coilcraft 0805HQ series (0.1–1000 nH), Mini-Circuits ADCH-80+ broadband choke, or wound ferrite bead
• Cap: ATC 600S series (high-Q RF caps), Murata GRM RF series, Johanson 0402 RF caps
• Self-resonant frequency (SRF) of choke must be >3× f_high for adequate isolation
• Add a 100Ω series resistor between DC supply and choke to reduce common-mode noise

Bias Tee Design Guide

A bias tee is a three-port network used to inject DC bias onto an RF signal path without disturbing the RF signal. It combines an RF choke (inductor) and a DC-blocking capacitor to route DC current to the active device while keeping the RF path clean.

RF Choke Selection

The choke must present a high impedance at all RF frequencies of interest. A common rule is that Z_choke = 2πf·L should be at least 10–100× Z₀ at the lowest RF frequency. The self-resonant frequency (SRF) of the choke must be well above the highest RF frequency — below SRF the inductor behaves inductively, above SRF it becomes capacitive and loses its choking ability.

DC-Blocking Capacitor Selection

The blocking capacitor must present low impedance at RF (to pass the signal with minimal loss) while blocking DC completely. The capacitor insertion loss is determined by its impedance relative to Z₀: IL = 20·log(√(1 + 1/(2πf·C·Z₀)²)). High-Q RF capacitors (ATC 600S, Murata GRM series) are preferred — standard ceramic capacitors have too much ESR and parasitic inductance at microwave frequencies.