Phase-Locked Loop Q&A

A Phase-Locked Loop (PLL) is a feedback circuit that makes one signal's frequency and phase lock on to another signal. Think of it like cruise control in a car — the car (VCO output) is told to follow a target speed (reference frequency), and a feedback sensor (phase detector) constantly measures the error and corrects it.

The PLL solves two problems at once: frequency multiplication (producing a high, stable output frequency from a cheap, low-frequency crystal reference) and frequency synthesis (generating many precise output frequencies by changing the divider value N). Without PLLs, every radio would need a separate crystal for every channel — impractical for a phone that supports hundreds of LTE channels.

• Phase Detector (PD) / Phase-Frequency Detector (PFD): Compares the phase (and frequency) of the reference signal to the divided-down VCO output. Produces an error signal proportional to their difference. If VCO is too fast, output says "slow down". If too slow, "speed up".
• Loop Filter (LF): Smooths the error signal from the PFD. Removes high-frequency switching noise (reference ripple) before it modulates the VCO. The loop filter's bandwidth determines how quickly the PLL responds to changes and how much reference spurious noise reaches the VCO.
• Voltage-Controlled Oscillator (VCO): Generates the output frequency. Its frequency is controlled by the voltage from the loop filter — higher voltage = higher frequency (or lower, depending on design). The VCO is the noisiest element in the PLL.
• Feedback Divider (÷N): Divides the VCO output frequency by N before feeding it back to the PFD. When locked, f_out/N = f_ref, so f_out = N × f_ref. Changing N tunes the output frequency in steps of f_ref.

Unlocked: The VCO is running at some arbitrary frequency. The PFD sees a large frequency difference and generates large, rapid corrections. The VCO frequency sweeps. The output is not at the desired frequency — not usable.

Locked: The VCO frequency exactly equals N × f_ref. The PFD sees only a small, constant phase error (ideally zero). The loop filter output is a stable DC voltage. The output is a clean, stable frequency. This is the normal operating state.

Acquisition (how it gets from unlocked to locked):

1. At power-up, VCO is at some random frequency. PFD detects huge frequency error.
2. PFD generates large charge pump current pulses — the loop filter charges/discharges rapidly.
3. VCO frequency sweeps toward f_ref × N. This is called frequency acquisition.
4. Once the VCO is close enough (within the pull-in range), the phase lock takes over — phase acquisition.
5. Small oscillations around the target frequency damp out — the PLL settles.

A charge pump PLL replaces the analogue multiplier phase detector with a PFD followed by a charge pump circuit. The PFD produces two digital signals: UP and DOWN pulses. The charge pump converts these into current: UP pulse → current +Icp flows into the loop filter capacitor. DOWN pulse → current −Icp flows out.

Why it dominates:

• The charge pump integrates the phase error on the capacitor — this acts as a natural integrator in the loop, giving zero steady-state phase error (Type 2 PLL).
• Easy to change divider N (digital) without changing any analogue circuit.
• Works over a wide frequency range — the PFD detects frequency difference, not just phase.
• Fully integratable on CMOS — the charge pump, PFD and divider are all digital-friendly.

The VCO is an oscillator whose output frequency is controlled by an input voltage. Higher control voltage = higher output frequency (for a typical varactor-tuned LC VCO). The VCO is the element that actually generates the RF signal in the synthesiser.

Why Kv matters:

• Loop bandwidth: Loop bandwidth ∝ Kv. Larger Kv = faster loop but more phase noise close to carrier (more pushing).
• Supply pushing: High Kv means power supply noise also modulates the frequency — a 1 mV supply ripple causes Kv × 0.001 Hz of frequency modulation. This is a major problem at mmWave.
• Phase noise: For a given tuning voltage noise (from charge pump), larger Kv = more frequency deviation = worse phase noise in-band.
• Tuning range: f_max − f_min = Kv × (Vmax − Vmin). Must cover all required frequencies.

An ideal oscillator produces a perfect sine wave at exactly one frequency — a single spike in the frequency domain. A real oscillator has random fluctuations in its phase — like a clock that sometimes runs slightly fast or slightly slow. These phase fluctuations cause the frequency spike to spread out, with "skirts" of noise around the carrier.

Phase noise measures the power of these noise skirts at a specific offset from the carrier, normalised to 1 Hz bandwidth.

Why it matters: Phase noise from your LO leaks into the received signal via the mixer. If you're receiving a weak signal at 2400.001 GHz while a strong interferer sits at 2400.01 GHz, the phase noise skirt of your LO can "reciprocal mix" with the strong interferer and create noise right on top of your weak signal — killing reception. This is called reciprocal mixing.

Breaking down each term physically:

• 2FkT/P_sig: The noise floor contribution — thermal noise from the active device, normalised by the signal power. Higher signal power → less phase noise. This is why oscillators benefit from running at higher power levels. F accounts for the excess noise of the transistor beyond thermal.
• (f_0/(2Q_L·f_m))²: The resonator upconversion effect. At close-in offsets (small f_m), the resonator's finite Q causes noise to be much higher. A higher Q resonator (crystal, SAW, FBAR) suppresses this term dramatically. Explains why crystal oscillators have spectacularly good phase noise close-in — crystal Q can be 100,000 vs 20 for an LC tank.
• 1 + f_c/f_m: The 1/f (flicker) noise upconversion. Transistors have 1/f noise that gets upconverted to phase noise around the carrier. f_c is the flicker corner frequency — below this offset, phase noise falls as 1/f³ instead of 1/f².

The PLL has two competing noise sources that produce opposite shapes in the phase noise plot:

• Inside the loop bandwidth: Phase noise is dominated by the reference source noise, multiplied up by 20·log(N). The PLL actively tracks the reference — and also tracks its noise. The PLL "cleans up" VCO noise inside the bandwidth but cannot do anything about reference noise.
• Outside the loop bandwidth: The feedback loop cannot respond fast enough to correct the VCO. Phase noise is dominated by the free-running VCO noise. Ideally this falls as 1/f² or 1/f³.

The phase noise hump appears near the loop bandwidth transition. It comes from a combination of the VCO noise rising (as the loop's suppression reduces) and a peaking in the loop's transfer function if the phase margin is insufficient (under-damped loop). A well-designed PLL has a peaking of <1–2 dB at the bandwidth transition.

Phase noise L(f) is a spectral density — noise at each frequency offset. But for system design you need a single number: how much total phase variation does the oscillator have? That's the integrated phase noise.

Jitter is the time domain version of phase noise — how much the zero crossings of the signal vary from their ideal positions. ADCs, SerDes links, and digital communications all specify jitter directly in picoseconds.

• 1 GHz clock with −100 dBc/Hz at 10 kHz offset, −130 dBc/Hz at 1 MHz: integrated jitter ≈ 1–2 ps typically
• WiFi local oscillator at 2.4 GHz: typically <0.5° RMS phase noise → <0.6 ps
• 5G mmWave at 28 GHz: needs <0.1° RMS for 256-QAM → <20 fs — extremely challenging

Inside the PLL bandwidth, the output phase noise equals the reference noise multiplied by N² — or in dB: the reference phase noise plus 20·log₁₀(N).

Physical intuition: The divider measures phase in units of 1/N of the VCO period. A given phase error in the reference looks N times bigger when multiplied up to the VCO frequency. The PLL tries to match the divided VCO phase to the reference phase — any reference phase noise appears amplified by N at the output.

Alternatively: the feedback path divides the frequency by N. To keep a constant loop gain, any noise going through the forward path (to the VCO) must be N× larger to overcome the N× attenuation of the feedback path. This gain of N appears squared in power terms → 20 log N in dBc/Hz.

The loop filter has three jobs: (1) smooth the charge pump current pulses into a clean DC control voltage; (2) set the loop bandwidth (how fast the PLL responds); (3) control the phase margin (stability) of the feedback loop.

The zero introduced by R1 (at frequency 1/(R1·C1)) is critical for stability — without it, the loop has only phase-lagging poles and will oscillate. R1 provides phase lead (phase margin) to stabilise the feedback loop.

• Phase margin: Should be 45°–65° for good transient behaviour. <30° = ringing and hump in phase noise. >75° = too sluggish.
• C2 ≪ C1: C2 is typically C1/10. It attenuates the reference spur by about 20·log(C1/C2) dB but also reduces phase margin — must recompute.

The optimal bandwidth is where VCO noise and reference×N noise are equal — minimises total integrated phase noise. For most 2.4 GHz PLLs this is typically 50–100 kHz.

Phase margin is a measure of how stable the feedback loop is. It tells you how many extra degrees of phase shift the loop could tolerate before it starts oscillating. Phase margin ≥ 45° is the standard target for a well-behaved loop.

In a charge pump PLL, the open loop transfer function has two poles from the loop filter and the VCO integration, plus a zero from R1 in the loop filter:

• Two poles contribute −180° of phase at all frequencies → loop is inherently on the edge of instability
• R1 introduces a zero at ω_z = 1/(R1×C1) → adds +90° of phase in the region above ω_z → this is the phase margin contribution

Reference spurs are discrete tones that appear in the PLL output spectrum at offsets of ±f_ref, ±2·f_ref, etc. from the carrier. They look like small satellite peaks sitting exactly f_ref away from the main carrier.

Causes:

• Charge pump mismatch: UP and DOWN currents are not perfectly equal. When locked, the PFD produces short equal UP and DOWN pulses that cancel on average. But if Iup ≠ Idn, a net current pulse at f_ref repetitively modulates the VCO — creating spurs.
• Charge pump dead zone avoidance: Modern PFDs deliberately produce a small overlap between UP and DOWN pulses to avoid the dead zone. These narrow pulses at f_ref modulate the VCO.
• Substrate coupling: The reference clock couples into the VCO supply or substrate, directly frequency-modulating it.

Why harmful: Spurs at f_ref offset will mix with any blocker that happens to be f_ref away from the desired channel. In LTE (f_ref = 26 MHz), a spur at 26 MHz offset could be right in an adjacent LTE channel. Typical requirement: spurs < −60 dBc (often < −70 dBc for modern standards).

1. Increase loop filter attenuation at f_ref: Add more capacitance (C2, or a 3rd-order filter stage). Each extra pole gives ~20 dB/decade more attenuation at the spur frequency.
2. Reduce charge pump current mismatch: Use better-matched transistors in the charge pump (careful layout, longer channel devices, common centroid). This reduces the fundamental cause — the net current pulse at f_ref.
3. Use higher reference frequency: If f_ref is doubled, the spur moves to 2× the offset where the loop filter provides more attenuation. This is one reason fractional-N PLLs (which use high f_ref) often have lower spurs than integer-N.
4. Isolation and shielding: Physically isolate the reference oscillator and divider from the VCO. Use separate supply domains, substrate contacts, and metal shielding to reduce substrate coupling.
5. Resample trick: Use a DFF-based PFD with a reset that is delayed to allow UP and DOWN pulses to fully cancel before the VCO modulation. Reduces the effective pulse width hitting the VCO.
6. Digital spur cancellation: Inject a precisely calibrated current into the loop filter to cancel the charge pump current imbalance. Used in advanced fractional-N synthesisers.

In an integer-N PLL, the feedback divider uses a whole number N. The output frequency is exactly N × f_ref, so the minimum frequency step = f_ref. If you need 100 kHz channel spacing, f_ref = 100 kHz. But then a 1 GHz output needs N = 10,000 → 20·log(10000) = +80 dB phase noise penalty. Also, the loop bandwidth must be ≤ f_ref/10 = 10 kHz → very slow lock.

In a fractional-N PLL, the divider alternates between N and N+1 (or more values) so the average division ratio is a fraction. If it divides by 10 half the time and 11 half the time, the average is 10.5 — giving resolution finer than f_ref.

Example: Need 1.8 GHz output with 100 kHz resolution:
Integer-N: f_ref = 100 kHz, N = 18000 → 20·log(18000) = +85 dB noise penalty
Fractional-N: f_ref = 13 MHz, N ≈ 138.46 → 20·log(138) = +43 dB noise penalty — 42 dB improvement!

A simple fractional-N PLL that alternates between N and N+1 does so in a periodic pattern. For example, dividing by 10 three times then 11 once (average 10.25) creates a periodic pattern at f_ref/4. This periodic modulation creates fractional spurs — discrete tones at sub-multiples of f_ref. They can be very close to the carrier and are often worse than reference spurs.

A Sigma-Delta (ΣΔ) modulator is the clever solution. Instead of a simple periodic pattern, it randomises the sequence of N and N+1 (and N+2, N+3 etc.) in a pseudo-random way that spreads the quantisation noise across all frequencies rather than concentrating it in spurs. The ΣΔ modulator pushes the quantisation noise to high frequencies (noise shaping), where the PLL loop filter can attenuate it.

A multi-modulus divider (MMD) is a digital counter that can divide by different integer values (e.g. 2, 3, 4, 5) depending on a digital control input. In a fractional-N synthesiser, the ΣΔ modulator feeds a sequence of divide values to the MMD. The MMD switches its division ratio cycle-by-cycle, averaging to the desired fractional value.

The MMD is implemented as a chain of 2/3 cells or 2/3/4 cells. Each cell can swallow or skip a pulse from the VCO. By cascading M cells you get a division ratio range of 2^M and fine resolution. The highest-speed cell (first in chain) is the most power-hungry and must operate at the full VCO frequency — the bottleneck in mmWave synthesisers.

Lock time is how long the PLL takes to settle to the new output frequency after a frequency hop command. It must be fast enough for the radio system — Bluetooth hops 1600 times/second and needs <100 µs lock time.

Factors that determine lock time:

• Loop bandwidth f_BW: Wider = faster lock. The single biggest lever.
• Frequency step size: Larger step → longer pull-in time. Must check the non-linear pull-in range.
• Phase margin: Under-damped loops (PM < 45°) ring and take longer to settle even though they have faster initial response.
• VCO tuning range: If the new frequency is near the edge of the VCO tuning range, Kv may be lower → effectively narrower loop bandwidth → slower lock.

A modern smartphone contains 10–20 PLLs performing different functions:

1. LTE/5G frequency synthesiser: Generates the LO for the RF mixer in the transmitter and receiver. Must cover 600 MHz to 5 GHz (sub-6) or 24–47 GHz (mmWave) with fine resolution (<1 kHz) and very low phase noise.
2. WiFi/Bluetooth synthesiser: Generates 2.4 GHz or 5 GHz LO for the WLAN radio. Must switch between channels quickly for Bluetooth frequency hopping.
3. Clock synthesis for the CPU/GPU: The processor PLL multiplies a slow crystal reference (e.g. 38.4 MHz) to generate the high-speed CPU clock (e.g. 3 GHz). Also provides fractional rates for power management (run at 1.2 GHz to save battery).
4. USB/PCIe clock recovery: High-speed serial interfaces need a PLL to recover the clock from the data stream (Clock and Data Recovery, CDR).
5. Camera clock: The MIPI interface between the camera sensor and the processor uses a PLL to generate precise pixel clocks.
6. Display clock: MIPI DSI to the display panel requires a PLL for timing.
7. GPS receiver: The baseband processing chip uses a PLL to track the satellite code phase — essentially a PLL locked to the GPS signal itself.

The reference oscillator is the foundation of all frequency accuracy in a radio. Its frequency error multiplies up by N to the output — a 1 ppm error in the reference becomes a 1 ppm error in the LO (e.g. 1.8 GHz × 1 ppm = 1.8 kHz error). Standards like LTE require frequency error <0.1 ppm.

• Standard crystal (XO): Accuracy ±20–50 ppm, temperature sensitivity ≈ ±20 ppm over −40°C to +85°C. Too inaccurate for cellular standards.
• TCXO (Temperature Compensated Crystal Oscillator): Uses a temperature sensor and a compensation network to cancel the crystal's temperature coefficient. Achieves ±0.5–2 ppm over full temperature range. Used in most phones. Costs ~$0.50–$2.
• OCXO (Oven-Controlled Crystal Oscillator): Keeps the crystal in a temperature-controlled oven at exactly the crystal's turnover temperature. Achieves ±0.001–0.01 ppm stability. Used in base stations, GPS references, test equipment. Costs ~$50–$500, consumes 1–5W for the oven heater.

A varactor (variable capacitor) is a diode whose junction capacitance varies with the applied reverse bias voltage. As you increase the reverse voltage, the depletion region widens and capacitance decreases. This voltage-controlled capacitance, placed in the LC tank of the VCO, directly controls the resonant frequency.

What limits the tuning range:

• Capacitance ratio C_max/C_min: A hyperabrupt varactor gives a ratio of 5–10:1. f_max/f_min = √(C_max/C_min) = √5–√10 → only 40–70% tuning range.
• Parasitic capacitances: Fixed parasitics from metal routing, transistor drain/gate, and bond pads reduce the relative contribution of the varactor → less frequency swing.
• Q degradation at extremes: Varactor Q is lowest at low voltages (high capacitance). Running the VCO at the low-voltage end of the tuning range increases phase noise.

VCO pushing is the change in output frequency caused by a change in supply voltage. The transistor's drain-source voltage affects the drain capacitance (C_ds), which shifts the VCO resonance. Even a 1 mV supply ripple can cause frequency modulation at the ripple frequency.

VCO pulling is the frequency shift caused by a changing load impedance at the VCO output. If the load reflection coefficient changes (e.g. the PA's input impedance varies with signal level, antenna mismatch changes), the VCO resonance shifts. This is why a buffer amplifier between the VCO and the PA/mixer is essential.

Reducing pushing:

• Use a dedicated, well-regulated VCO supply (LDO or supply regulator)
• Use differential VCO topology (rejects common-mode supply noise)
• Use cascode transistors in the VCO core (reduces supply sensitivity)

Reducing pulling:

• Always put a buffer amplifier (isolator) between VCO and load
• Use two stages of buffering for PA-VCO coupling
• Differential topology rejects common-mode injection on substrate

An injection-locked oscillator is a free-running oscillator that, when a signal is injected close to its natural frequency, "locks" to the injected signal — adopting exactly the frequency and a fixed phase offset relative to the injection. It's a one-component PLL — no PFD, loop filter, or divider needed.

Key differences from a PLL:

• ILO: Narrowband (lock range limited by Q), extremely fast "lock" (near instantaneous since no loop filter), very low power (no PFD/CP/divider), very low phase noise inside the locking range (inherits reference phase noise directly).
• PLL: Wideband tuning via divider, controlled loop bandwidth, programmable output frequency, but more complex and power-hungry.

ILOs are used as frequency dividers at mmWave (dividing 60 GHz by 2 to get 30 GHz) where digital dividers are too slow and power-hungry. They're also used as clock multipliers in optical communications.

Phase noise from the LO degrades the receiver in two ways: reciprocal mixing and EVM degradation.

Reciprocal mixing: When a strong interferer is present f_offset away from the desired signal, the phase noise skirt of the LO at that offset mixes with the strong interferer, downconverting it as noise on top of your desired channel. The noise power at baseband from this effect = P_interferer + L(f_offset) + 10·log(BW).

EVM degradation: In QAM systems (WiFi, LTE, 5G), integrated phase noise directly rotates constellation points, increasing EVM. 256-QAM needs EVM < 3.5% → requires integrated phase noise < 1° RMS → tight phase noise specification over the signal bandwidth.

A standard PLL suppresses frequency modulation of the VCO — that's how it maintains a stable frequency. So if you try to FM-modulate by varying the VCO tuning voltage directly, the PLL will fight against you and remove the modulation inside the loop bandwidth.

Two-point modulation applies the modulation signal at TWO points simultaneously:

• High-frequency path: Directly to the VCO tuning voltage (instant response, but PLL will suppress it for low-frequency components)
• Low-frequency path: To the reference divider ratio (which the PLL tracks, even for slow changes)

This allows efficient FM modulation of the PLL output across a wide bandwidth — used in GSM/EDGE transmitters (GFSK modulation), Bluetooth (GFSK), and DECT phones. The technique, called "type-II modulation" or "polar transmitter", allows the PLL itself to be the modulator — eliminating a separate upconverter mixer.

In a conventional PLL, the VCO output is divided by N before phase comparison. The divider is a major phase noise contributor — it operates at high speed and adds broadband noise that appears directly at the PLL output.

In a sub-sampling PLL, the phase detector is replaced by a sample-and-hold circuit that samples the VCO output directly at the reference frequency — comparing the VCO phase at f_ref intervals without dividing the frequency. No divider means no divider noise.

Tradeoffs of SSPLL:

• Only works when the PLL is already near lock (no frequency detection) — needs an auxiliary FLL for initial lock acquisition
• Sensitive to reference clock harmonics (samples at f_ref, aliases harmonics)
• Charge pump noise still present — must use large sampling capacitors

Phase noise is measured using a spectrum analyser or a dedicated phase noise analyser:

1. Place the carrier on the centre of the screen, resolution bandwidth (RBW) set to a few percent of the offset of interest
2. Measure the carrier power (dBm)
3. Move to the desired offset frequency, measure the noise power in the RBW
4. Normalise: L(f) = Noise_power_dBm − Carrier_dBm − 10·log(RBW)
5. Subtract the analyser's own noise floor (which limits measurement at low phase noise)

Limitations of spectrum analyser method:

• Analyser has its own phase noise — limits measurement to signals with L(f) > analyser phase noise (typically > −140 dBc/Hz for a good analyser)
• Carrier must not drift or the noise floor measurement is corrupted
• For very close-in offsets (<1 kHz), RBW must be very narrow → long sweep time → thermal drift matters

1. Is the reference oscillator running? Check f_ref on a spectrum analyser or oscilloscope. Correct amplitude, frequency, duty cycle? Many lock failures start here.
2. Is power applied correctly? VCO supply, PFD supply, charge pump supply — each may be on a separate rail. Check with a multimeter.
3. Is the VCO tuning range wide enough? Scope the Vtune pin. Is it sweeping across the full supply range (e.g. 0–3.3 V) or stuck at a rail? If stuck at the positive rail, VCO can't go high enough — Kv or tuning range problem. Stuck at GND — VCO can't go low enough.
4. Is the PFD/charge pump working? Check the LD (lock detect) output if available. On an oscilloscope, look at the CP output — when unlocked it should show rapid UP/DOWN pulses trying to drive the loop.
5. Is N programmed correctly? Read back the SPI register that sets N. A wrong N means the PLL locks to the wrong frequency or out of the VCO's range.
6. Is there a sign error in the loop? If the PFD polarity or CP polarity is wrong, the loop has positive feedback → VCO will rail and won't lock. Scope Vtune — does it go up when you'd expect it to go down?
7. Is the loop bandwidth too narrow? VCO noise may push the signal around faster than the loop can track — check if the frequency seems to wander slowly vs jump.

1. Fractional spurs (fractional-N PLLs): Imperfect ΣΔ noise shaping or insufficient dithering leaves residual periodic patterns in the divider sequence → tones at fractional offsets from the carrier (e.g. f_ref/3, f_ref/5 etc.).
2. Power supply harmonics coupling: DC-DC converter switching noise (e.g. 1 MHz buck converter) couples into the VCO through substrate or supply, creating spurs at the converter switching frequency and its harmonics regardless of f_ref.
3. Crystal overtone crosstalk: The crystal reference oscillator runs at its fundamental and also has energy at 3rd, 5th overtones. These can couple into the VCO output and appear as spurs at 3× and 5× the crystal frequency.
4. Digital clock coupling: Clocks from other digital circuits on the chip (baseband processor, USB clock, display clock) can couple into the VCO through substrate. Appear as spurs at those clock frequencies.
5. Spur from other PLL: In a multi-PLL chip (e.g. phone SoC), the output of one PLL can couple into another through substrate, creating cross-PLL spurs at beat frequencies.

An all-digital PLL (ADPLL) replaces the analogue components (PFD, charge pump, loop filter, analogue VCO) with digital equivalents:

• PFD → Time-to-Digital Converter (TDC): measures the time difference between reference and divided-VCO edges to picosecond resolution
• Charge pump + Loop filter → Digital Loop Filter (DLF): a digital IIR/FIR filter computed in logic
• Analogue VCO → Digitally-Controlled Oscillator (DCO): an LC oscillator with a switched capacitor bank controlled by a digital word

Advantages in advanced CMOS (5nm, 3nm):

• Scales with process — digital logic gets faster and smaller, but analogue components (caps, resistors) don't scale well
• No analogue-sensitive layout constraints — loop filter is just logic
• Reconfigurable bandwidth, phase margin in firmware
• Built-in digital calibration eliminates charge pump mismatch spurs
• Better integration in digital VLSI flows

Designing a 28 GHz PLL is fundamentally different from a 2.4 GHz PLL:

1. VCO inductor Q: At 28 GHz, on-chip inductors have Q ≈ 15–25 (versus 10–15 at 5 GHz). Better Q improves phase noise, but inductors are tiny (≈50 pH) and extremely sensitive to layout.
2. First divider speed: The first divide-by-2 must operate at 28 GHz. Static CMOS dividers fail. Use CML (Current Mode Logic) or injection-locked dividers. Power consumption is 5–20 mW per stage.
3. Phase noise target: 256-QAM at 28 GHz with 400 MHz bandwidth requires integrated phase noise <1° RMS → approximately −88 dBc/Hz at 1 MHz offset. Very demanding.
4. VCO pushing (substrate): At 28 GHz, any 28 GHz signal coupling back into the VCO through the substrate causes severe injection pulling. Deep N-well, shielded inductors, differential topology are mandatory.
5. Tuning range: 5G NR uses n257 (26.5–29.5 GHz) and n258 (24.25–27.5 GHz). A single VCO must cover 3–5 GHz — over 15% fractional tuning range. Requires sub-band switching + varactor fine tuning.

Cycle slipping occurs when the phase error in a PLL exceeds 2π radians — the PFD "wraps around" and the lock is temporarily lost before the loop re-establishes phase lock. It looks like a brief frequency glitch.

When it occurs:

• Large frequency steps that exceed the pull-in range — the VCO can't slew fast enough and the divider output "skips" a reference edge
• Strong external noise that momentarily pushes the VCO phase beyond the tracking range
• Narrowband loop with large FM noise on the VCO — if VCO noise causes more than 2π phase deviation at the PFD, cycle slip
• Reference or VCO spurs that temporarily defeat lock

The Type of a PLL refers to the number of perfect integrators (poles at exactly s=0) in the open-loop transfer function.

Why Type 2 dominates: A Type 1 PLL has steady-state phase error when tracking a frequency ramp or step. For a frequency synthesiser that hops channels, each new channel would have a residual phase offset — unacceptable for QAM demodulation. A Type 2 PLL (charge pump design) drives the steady-state phase error to zero regardless of the frequency step, because the charge pump's capacitor retains exactly the voltage needed to hold the VCO at f_ref × N. No bleed resistor, no droop.

This is the classic PLL design walkthrough question. Here's a structured approach:

Step 1 — Define requirements: Output frequency 2400–2483 MHz (WiFi channels), channel spacing 5 MHz (IEEE 802.11b/g/n channels), phase noise < −100 dBc/Hz at 1 MHz (to meet EVM for 64-QAM), lock time < 200 µs (channel switching), reference spur < −60 dBc, supply 3.3 V or 1.8 V CMOS.

Step 2 — Choose architecture: Fractional-N with ΣΔ modulator. Reason: 5 MHz channel spacing with f_ref = 26 MHz (TCXO) → N ≈ 92.3 to 95.5, N is non-integer → fractional-N. This gives 20·log(93) = +39 dB noise multiplication vs +69 dB for integer-N with 1 MHz ref.

Step 3 — VCO design: LC VCO at 2.4 GHz with NMOS-PMOS cross-coupled pair. Inductive coil Q ≈ 15 on-chip. Target phase noise −130 dBc/Hz at 1 MHz offset free-running. Tuning range: 2380–2510 MHz (5% margin each side). Kv ≈ 30 MHz/V nominal.

Step 4 — Divider: 3rd-order ΣΔ MMD, divides by 92–96. Programmable via SPI. First divider cell at 2.4 GHz uses CML, remaining cells use CMOS.

Step 5 — Loop filter: Passive 3rd order. Target loop BW = 100 kHz (Bluetooth coexistence, moderate lock time). Icp = 400 µA, C1 = 4.7 nF, R1 = 3.3 kΩ, C2 = 470 pF, R2 = 1 kΩ, C3 = 100 pF. Phase margin ≈ 55°.

Step 6 — Verify: Simulate phase noise (ADIsimPLL or SpectreRF), check lock time (transient sim), check reference spur (100 kHz filter suppresses 26 MHz by 48 dB → spur ≈ −60 dBc — at limit, may need C3 increase).