Via Inductance Calculator
Compute PCB via inductance, self-resonant frequency and impedance at any target frequency. Supports single via, differential pair and anti-pad configurations. Essential for RF PCB design above 1 GHz.
L (nH) = 5.08 × h × [ln(4h/d) + 1] (single via)
L_diff (nH) = 5.08 × h × [ln(4h/d) + 1 − M/L] (differential — mutual inductance reduces net L)
Anti-pad capacitance:
C (pF) = 1.41 × εr × T × D / (D_ap − D) (T = copper foil thickness ≈ 0.035 mm typical)
Self-resonant frequency:
SRF = 1 / (2π√(LC)) Above SRF the via looks capacitive — avoid or use back-drilling
| Frequency | X_L (Ω) | X_C (Ω) | |Z| (Ω) | Regime |
|---|
PCB Via Inductance — Why It Matters Above 1 GHz
A PCB via is not just a hole — it is a small inductor, capacitor, and in some cases a resonator. At DC and audio frequencies this is irrelevant. Above 1 GHz, a typical through-hole via (0.3 mm drill, 1.6 mm board) has ~0.5–1.0 nH of inductance, which presents 6–12 Ω of inductive reactance at 10 GHz. For a 50 Ω signal path, this is a significant discontinuity that causes reflections, insertion loss, and phase error.
The Wadell Formula
The most widely used model for single-via inductance is: L (nH) = 5.08 × h × [ln(4h/d) + 1] where h is the via height (board thickness) in inches and d is the drill diameter in inches. In metric, substituting h and d in millimetres and dividing by 25.4 gives the same result. This formula comes from IPC-2141 and is accurate to within 10–20% for typical PCB vias up to the GHz range.
Anti-Pad Capacitance
Each layer where the via passes through a ground or power plane has a clearance hole (anti-pad) around the via. This creates a small capacitance between the via pad and the surrounding plane — typically 5–50 fF per layer. This capacitance forms an LC resonator with the via inductance. The self-resonant frequency (SRF) of this LC circuit is where the via changes from inductive behaviour (below SRF) to capacitive behaviour (above SRF). Operating near or above the SRF causes severe signal integrity problems.
Back-Drilling
A through-hole via that only carries signal between layers 1 and 4 on a 12-layer board has an unused "stub" from layer 4 to layer 12. This stub acts as an open-circuit transmission line resonator. At the frequency where the stub length equals λ/4, the via presents a short circuit to the signal — a deep notch in the transmission response. Back-drilling (controlled-depth drilling from the back of the board) removes the stub, eliminating this resonance. Vias with stubs shorter than λ/20 at the operating frequency are generally acceptable.
Design Rules for RF Vias
Keep vias short: Inductance scales linearly with via height (board thickness). Use thin boards or blind/buried vias for critical RF signals above 10 GHz.
Maximise drill diameter: L ∝ ln(4h/d) — larger drill diameters reduce inductance logarithmically. HDI microvias (0.1 mm drill, 0.2 mm total depth) have very low inductance (~0.1 nH) and are used in mmWave PCBs.
Use ground via fences: Surround signal vias with a ring of ground vias (spacing ≤ λ/20) to control the field distribution and reduce radiation and crosstalk.
Check f/SRF ratio: The operating frequency should be below 20% of the SRF for the via to behave as a simple inductor. Above 50% of SRF, the via impedance varies rapidly with frequency and should be avoided.