Calculators › Frequency Synthesis

PLL Synthesiser Calculator

Complete charge-pump PLL design tool. Compute N divider ratio, loop filter component values, loop bandwidth, phase margin, lock time and a full phase noise budget from reference through to VCO output.

// PLL Architecture
MHz
MHz
// Loop Filter & Charge Pump
mA
MHz/V
kHz
°
// Phase Noise Sources
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
// PLL Block Diagram
REF 10 MHz /R PFD +CP LPF C1 R2 C2 VCO 2400 MHz OUT /N N = 240 f_comp = 10 MHz Loop BW: 100 kHz Phase margin: 50°
// Frequency Plan Results
Divider Chain
Comparison frequency fcomp—
Integer N divider—
Fractional part (frac-N only)—
Actual output frequency—
Frequency error—
Channel step size—
Loop Filter (2nd-order passive)
C1 (main capacitor)—
R2 (series resistor)—
C2 (ripple suppression)—
Zero frequency ωz—
Pole frequency ωp—
Loop Dynamics
Open-loop BW (−0 dB crossover)—
Phase margin—
Lock time (est.)—
Reference spur offset—
// Phase Noise Budget at Output
SourcePN @ 10 kHzPN @ 1 MHzDominant?
In-band (<fL): reference & PLL floor dominate. Out-of-band (>fL): VCO dominates. Total = RSS of all contributors.
// Output Phase Noise vs Offset Frequency
Total output PN VCO free-running Reference (×20logN)
// Loop Filter Design Equations
Open-loop gain: G(s) = Icp·Kv·Z(s) / (2π·N·s)
Loop filter Z(s): (1+sR2C1) / (s·C1·(1+sR2C2/(C1+C2)))

Natural frequency: ωn = √(Icp·Kv·(C1+C2) / (2π·N·C1·C2·R2))
Zero: ωz = 1/(R2C1)  ·  Pole: ωp = (C1+C2)/(R2C1C2)

In-band PN (reference contribution):
Lout,in(f) = Lref(f) + 20·log(N)
Out-of-band PN (VCO): Lout,ob(f) = Lvco(f) (unattenuated)
Lock time: tlock ≈ 2π / (fL·2π) × ln(Δf/fres)

PLL Synthesiser Design Guide

A phase-locked loop (PLL) frequency synthesiser generates a precise high-frequency output locked to a stable low-frequency reference. The output frequency is f_out = N × f_ref/R, where N is the feedback divider ratio and R is the reference pre-divider. By changing N, the output frequency is changed in steps of f_ref/R (the comparison frequency f_comp).

Integer-N vs Fractional-N

In an integer-N PLL, N must be an integer, so the minimum channel step equals f_comp. To achieve 200 kHz channels at 900 MHz from a 10 MHz reference, R must be 50 (f_comp = 200 kHz) and N ≈ 4500. The large N degrades phase noise by 20·log(N) = 73 dB. Fractional-N PLLs allow non-integer N by rapidly switching between two integer values, achieving effective fractional division at the cost of fractional spurs. They allow a higher f_comp for the same channel step, reducing 20·log(N) and improving phase noise.

Loop Bandwidth Trade-off

The loop bandwidth sets the crossover between reference-dominated and VCO-dominated phase noise. Wide bandwidth suppresses VCO noise (good) but passes more reference noise and creates stronger reference spurs. Narrow bandwidth reduces reference noise contribution but allows the VCO to drift. Optimal loop bandwidth is where the reference contribution (L_ref + 20logN) equals the VCO contribution — this minimises total integrated phase noise.

Phase Margin and Stability

A second-order passive loop filter (C1, R2, C2) with a zero at ω_z = 1/(R2·C1) boosts phase margin. Without the zero, the loop has only 0° phase margin at crossover (unstable). Adding R2 provides phase lead; the zero should be placed at roughly half the crossover frequency. Target phase margin 45–60° for stable, well-damped response. Phase margin below 30° causes ringing and extended lock time.