Active Devices › Bias Networks
Transistor Bias Designer
Design DC bias networks for RF BJT, FET and HEMT transistors. Computes voltage divider resistors, stability factor S, bypass capacitor values, Q-point verification and nearest E24 resistor recommendations.
BJT Bias Specifications
V
mA
V
V
MHz
Voltage Divider Bias Circuit
BJT Bias Results
Q-Point Verification
Collector current ICQ—
Base current IBQ—
Emitter current IEQ—
VCEQ (calculated)—
Stability factor S—
Resistor Values
Emitter resistor RE—
Collector resistor RC—
Divider R1 (to VCC)—
Divider R2 (to GND)—
Nearest E24 R1—
Nearest E24 R2—
Bypass Capacitors
Emitter bypass CE (at f)—
Coupling cap CB (at f)—
DC supply bypass Csupply—
Design Equations
Stability factor S: S = (1 + RB/RE) / (1 + RB/(RE·β))
where RB = R1∥R2
Target S ≤ 10 for good thermal stability
Voltage divider: VB = VCC·R2/(R1+R2)
VE = VB − VBE · RE = VE/ICQ
Rule: Idivider ≈ 10×IBQ for good stability
Bypass cap: XCE = RE/10 at f → CE = 10/(2πf·RE)
Coupling cap: XCB = Zin/10 at f
where RB = R1∥R2
Target S ≤ 10 for good thermal stability
Voltage divider: VB = VCC·R2/(R1+R2)
VE = VB − VBE · RE = VE/ICQ
Rule: Idivider ≈ 10×IBQ for good stability
Bypass cap: XCE = RE/10 at f → CE = 10/(2πf·RE)
Coupling cap: XCB = Zin/10 at f
FET / HEMT Bias Specifications
V
mA
V
V
mA
MHz
FET Bias Results
Q-Point
Gate-source voltage VGSQ—
Drain current IDQ—
VDSQ (verified)—
Transconductance gm—
Bias Resistors
Source resistor RS—
Drain resistor RD—
Gate resistor RG—
Nearest E24 RS—
Bypass Capacitors
Source bypass CS—
RF choke on gate (if needed)—
FET Self-Bias Equations
JFET/depletion MOSFET self-bias:
ID = IDSS × (1 − VGS/VP)²
VGS = −ID × RS (source degeneration)
Solve iteratively: VGS = VP(1 − √(ID/IDSS))
→ RS = |VGS| / IDQ
pHEMT gate bias: Typically VGS = −0.5 to −0.8 V
Use negative supply or resistor divider from VDD
gm = 2√(ID·IDSS) / |VP|
ID = IDSS × (1 − VGS/VP)²
VGS = −ID × RS (source degeneration)
Solve iteratively: VGS = VP(1 − √(ID/IDSS))
→ RS = |VGS| / IDQ
pHEMT gate bias: Typically VGS = −0.5 to −0.8 V
Use negative supply or resistor divider from VDD
gm = 2√(ID·IDSS) / |VP|
Active Bias Network
An active bias circuit uses a second transistor (or op-amp) to hold the collector/drain current constant regardless of temperature and β variation. Far more stable than passive voltage divider bias.
V
mA
V
mA
Active Bias Results
Rset (sets reference current)—
Nearest E24 Rset—
Emitter degeneration RE—
Tempco improvement vs passive—
IC variation over β range—
Mirror current ratio: IC/Iref = emitter area ratio
Rset = (VCC − VBE) / Iref
Advantage: IC tracks VBE with temperature (both VBE change at −2 mV/°C), so IC is nearly constant
IC variation with β: ΔIC/IC ≈ 2/(β+2) — very small for β≥50
Rset = (VCC − VBE) / Iref
Advantage: IC tracks VBE with temperature (both VBE change at −2 mV/°C), so IC is nearly constant
IC variation with β: ΔIC/IC ≈ 2/(β+2) — very small for β≥50